Antti Kalanti
Aalto University
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Publication
Featured researches published by Antti Kalanti.
IEEE Journal of Solid-state Circuits | 2012
Mikail Yucetas; Mika Pulkkinen; Antti Kalanti; Jarno Salomaa; Lasse Aaltonen; Kari Halonen
In this paper, a charge-balancing accelerometer is presented. A hybrid interface topology is utilised to achieve high resolution, high linearity and low power supply sensitivity. The accelerometer consists of a micromechanical sensor element, a self-balancing bridge (SBB) open-loop readout, AC force feedback and ΔΣ ADC. The SBB converts acceleration to ratiometric voltage. The ratiometric output of the SBB is converted to the digital domain by the ADC. In order to achieve high resolution, a micromechanical sensor element with a high quality factor, Q, is utilised. The AC force feedback is used for damping the high Q to get a low settling time. The sensor interface is fabricated in a standard 0.35 μm CMOS process. The fabricated chip has an area of 6.66 mm2 and consumes 1 mA at a nominal supply voltage of 3.6 V. The sensor has a maximum DC nonlinearity of 1.3% over the commercial temperature range with an input range of ±1.15 g. The noise floor of the sensor is around 2 μg/√{Hz} and the signal bandwidth is 200 Hz. The bias instability is 13 μ g and the sensor gain variation is less than 5% in the 3-3.6 V supply range.
IEEE Journal of Solid-state Circuits | 2011
Lasse Aaltonen; Antti Kalanti; Mika Pulkkinen; Matti Paavola; Mika Kämäräinen; Kari Halonen
The interface for a capacitive 2-axis micro-gyroscope is implemented in a 0.35-μm HVCMOS technology with a total area of 4.3 mm2. The ASIC comprises the complete analog interface electronics for the gyroscope, while the focus of the design is in maintaining low supply current and in reducing the chip area. The paper reports the design of reference circuits, high-voltage generation, drive-loop and the capacitive open-loop readout circuits. The prototype sensor that is measured is assembled by directly wire-bonding the stacked dies comprising the interface electronics and the sensor element. The noise floors of the two sensors are 0.028°/s/√{Hz} for z-axis and 0.032°/s/√{Hz} for y-axis. The supply current of the chip is 2.2 mA from a 3 V-supply.
european solid-state circuits conference | 2010
Lasse Aaltonen; Antti Kalanti; Mika Pulkkinen; Matti Paavola; Mika Kämäräinen; Kari Halonen
The interface for a capacitive 2-axis micro-gyroscope is implemented in a 0.35-μm HVCMOS technology with a total area of 4.3 mm2. The ASIC comprises the complete interface electronics for the gyroscope, while the focus of the design is in maintaining low supply current and in reducing the chip area. The core of the interface is the pseudo-continuous-time sense readout with an analog output, together with a continuous-time drive loop. The biasing and high-voltage generation will also be introduced in the paper. For the sensor that was implemented, the noise floors are 0.012 °/s/vHz for x-axis and 0.062 °/s/vHz for y-axis. The supply current of the chip is 2.2 mA from a 3 V-supply.
biennial baltic electronics conference | 2010
Antti Kalanti; Lasse Aaltonen; Matti Paavola; Mika Kämäräinen; Mika Pulkkinen; Kari Halonen
As the complexity of the digital circuit blocks continues to increase, a power-on reset, POR, circuit is needed to initialize the digital logic to the known state at the start-up. This paper represents a POR with thresholds that are insensitive to the rise time of the supply voltage. This is achieved by generating the POR pulse with a constant current reference circuit. Moreover, current mirroring is used to improve hysteresis. The designed POR has a quiescent current of 3.1 µA (VDD=3.6 V) and operates with supplies ranging from 3 V to 3.6 V. The area of the circuit is 109.9 µm × 106.65 µm and the chip was implemented with triple-well 0.35 µm HVCMOS process.
conference on ph.d. research in microelectronics and electronics | 2011
Mikail Yucetas; Lasse Aaltonen; Mika Pulkkinen; Antti Kalanti; Kari Halonen
This paper presents a differential SC second-order single-bit ΔΣ analog-to-digital converter (ADC). The converter has nominal conversion rate of 100 kS/s with OSR of 1000. Differential converter topology is used. This leads to lower second order harmonic and lower offset voltage compared to single ended topology. Together with SC implementation, the differential converter also makes it possible to use high impedance common mode reference voltages for low power operation. Chopper stabilization has been used to decrease offset and low frequency noise. The converter is designed and will be implemented in a 0.35 µm CMOS process with a total active area of 0.24 mm2. Typically, it consumes 60 µA from a 3.3 V supply.
International Journal of Electrical Power & Energy Systems | 2014
Suvi Lehtimäki; Miao Li; Jarno Salomaa; Juho Pörhönen; Antti Kalanti; Sampo Tuukkanen; Petri S. Heljo; Kari Halonen; Donald Lupo
Archive | 2010
Jarno Salomaa; Mikail Yucetas; Antti Kalanti; Lasse Aaltonen; Kari Halonen
european solid-state circuits conference | 2011
Mikail Yucetas; Lasse Aaltonen; Mika Pulkkinen; Jarno Salomaa; Antti Kalanti; Kari Halonen
PRIME | 2011
Antti Kalanti; Lasse Aaltonen; Mikail Yucetas; Mika Pulkkinen; Matti Paavola; Mika Kämäräinen; Kari Halonen
PRIME | 2011
Mikail Yucetas; Lasse Aaltonen; Mika Pulkkinen; Antti Kalanti; Kari Halonen