Matti Paavola

A Micropower

In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer is presented. The IC is implemented in a 0.25-mum CMOS process. The fully-integrated sensor interface is based on a DeltaSigma sensor front-end that operates mechanically in an open-loop configuration and converts the acceleration signals directly into the digital domain, thus avoiding the use of separate analog-to-digital converters. A detailed analysis with transfer functions is presented for the front-end circuit. Furthermore, the interface IC includes a decimator, a frequency reference, a clock generator for the front-end, a voltage and current reference, the required reference buffers, and low-dropout regulators (LDOs) needed for system-on-chip power management. The interface IC provides operating modes with 12-bit resolution for 1 and 25 Hz signal bandwidths. The former is optimized for very low power dissipation at the cost of reduced bandwidth, and is intended for example for activity monitoring in otherwise powered-off devices. The chip, with a 1.73 mm2 active area, draws typically 21.2 muA in the 1 Hz mode, and 97.6 muA in the 25 Hz mode, from a 1.2-2.75 V supply. In the 1 and 25 Hz modes with a plusmn 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 1080, 1100 and 930 mug/radic{Hz}, and 360, 320 and 275 mug/radic{Hz} , respectively. The implemented prototype achieves competitive figures of merit (FOMs) compared to the other published or commercially available, low-g, low-power accelerometers.

\Delta\Sigma

In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.13- BiCMOS process is presented. The sensor interface consists of a front-end that converts the acceleration signal to voltage, two algorithmic ADCs, two frequency references, and a voltage, current, and temperature reference circuit. Die area and power dissipation are reduced by using time-multiplexed sampling and varying duty cycles down to 0.3%. The chip with a 0.51 active area draws 62 from a 1.8 V supply while sampling temperature at 100 Hz, and four proof masses, each at 1.04 kHz. With a 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 482 , 639 , and 662 , respectively.

-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

The interface for a capacitive 2-axis micro-gyroscope is implemented in a 0.35-μm HVCMOS technology with a total area of 4.3 mm2. The ASIC comprises the complete analog interface electronics for the gyroscope, while the focus of the design is in maintaining low supply current and in reducing the chip area. The paper reports the design of reference circuits, high-voltage generation, drive-loop and the capacitive open-loop readout circuits. The prototype sensor that is measured is assembled by directly wire-bonding the stacked dies comprising the interface electronics and the sensor element. The noise floors of the two sensors are 0.028°/s/√{Hz} for z-axis and 0.032°/s/√{Hz} for y-axis. The supply current of the chip is 2.2 mA from a 3 V-supply.

A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

In this paper, measurement results for a micropower 2 MHz CMOS frequency reference circuit fabricated with a 0.13 mum CMOS process are presented. This frequency reference circuit, based on source-coupled CMOS multivibrator, provides the clock signal for a read-out circuit of a capacitive sensor. In addition to low power consumption, good frequency stability is required. Supply independent biasing and symmetrical loads are used to optimize the frequency stability. The typical power consumption is 3.0 muW at room temperature with 1.8 V supply voltage. When properly calibrated, the frequency stays within plusmn2.5% of the nominal oscillation frequency in the operating voltage range of 1.8-2.5 V (with plusmn10% variation) over a temperature range from -35 to +85 degC. The measured phase noise and jitter agree well with the simulations

A 2.2 mA 4.3 mm

This paper presents the measurement results of a micropower switched-capacitor front end that was designed for three-axis capacitive microaccelerometers. The designed front end can reduce the distorting effects of the electrostatic forces and can be used in single-ended and differential modes. The front end was realized with a 0.13-mum bipolar complimentary metal-oxide-semiconductor process. The silicon area of the front end is 0.30 mm2. The measurements show that the functionality of the front end follows the theory in both modes. Consuming 20 muA from a 1.8-V supply, it achieves noise densities of 424, 607, and 590 mug/radic(Hz) in the x-, y-, and z-directions, respectively, when each mass is sampled at 1 kHz in the differential mode.

^{2}

The paper presents a DeltaSigma sensor for a capacitive micro-accelemeter. The prototype was fabricated with a 0.25 mum CMOS technology with MIM capacitors. The silicon area of the front-end is 0.49 mm2. The chip was combined with an external plusmn2g capacitive 3-axis accelerometer on a PCB.This DeltaSigma sensor front-end IC draws 1.5 muA from a 1V supply while sampling three proof masses, each at 4.096 kS/s.

ASIC for a 1000

In this paper, we describe the design of a 2 MHz CMOS frequency reference circuit based on a relaxation oscillator. The circuit provides the clock signal for a read-out circuit of a capacitive sensor. The frequency reference circuit is always active, thus low power consumption is an essential requirement. Supply independent biasing was used to allow supply voltages of 1.8-2.5 V without re-calibration. Simulations showed that the circuit consumes 3.0 /spl mu/W with 1.8 V supply voltage and stays within /spl plusmn/10% of the nominal oscillation frequency in the operating voltage range and at temperatures from -40 to 85/spl deg/C. A jitter approximation of /spl Delta/t/sub max/ /spl ap/ 5 ns and phase noise performance were obtained. The relative importance of different noise sources on phase noise are highlighted on the basis of phase transfer simulations. The circuit is being fabricated in a 0.13 /spl mu/m CMOS process.

^{\circ}

An interface ASIC for a capacitive 3-axis micro-accelerometer is implemented in a 0.13μm CMOS process. Die area and power dissipation are reduced by using time-multiplexed sampling and duty cycles down to 0.3%. The chip with 0.51 mm2 active area draws 62μA from a 1.8V supply while sampling 4 proof masses, each at 1 kS/s. With a plusmn4g capacitive 3-axis accelerometer, the measured noise in the x, y and z directions is 460μg/radicHz, 550(μg/radicHz and 550μg/radicHz, respectively.

/s 2-Axis Capacitive Micro-Gyroscope

In this paper, a micropower low-dropout regulator (LDO) for a low-power capacitive sensor interface fabricated in a 0.25 mum BiCMOS process is presented. The LDO with on-chip voltage and current references, and an on-chip programmable load capacitor, occupies an active silicon area of 0.18 mm2. It is stable with zero load current over the load capacitance range from 0 to 1 nF. The input voltage range extends from 1.2 to 2.75 V, while the designed output voltage is 1.0 V. The measured quiescent current of the LDO including the on-chip references is 7.6 muA. According to the measurements, the regulated output has a temperature coefficient (TC) of 57.2 ppm/degC, a line regulation of 2.71 mV/V, and a load regulation of 1.64 mV/mA. The rms output noise integrated over the bandwidth ranging from 1 Hz to 100 kHz is 1.365 mV.

A 3 /spl mu/W, 2 MHz CMOS frequency reference for capacitive sensor applications

In this paper, a nanopower CMOS frequency reference designed with a 0.25-mum BiCMOS process for an ultra- low-power capacitive sensor interface is presented. Due to the low supply voltage of 1 V, two parallel frequency references based on source-coupled CMOS multivibrators are used to implement the two required operating modes. In mode 1, when driving a 1 pF capacitive load at 24.6 kHz, the frequency reference consumes 210 nA. In mode 2, driving the same load at 307.2 kHz consumes 660 nA, respectively. Typical simulated frequency stabilities over the temperature and supply voltage ranges in modes 1 and 2 are plusmn10.7% and plusmn6.1 %, respectively. Simulated phase noises at 10 kHz offset frequency in mode 1, and at 100 kHz offset frequency in mode 2, are approximately -67 dBc/Hz and -68 dBc/Hz, respectively.