Mikail Yucetas

A High-Resolution Accelerometer With Electrostatic Damping and Improved Supply Sensitivity

In this paper, a charge-balancing accelerometer is presented. A hybrid interface topology is utilised to achieve high resolution, high linearity and low power supply sensitivity. The accelerometer consists of a micromechanical sensor element, a self-balancing bridge (SBB) open-loop readout, AC force feedback and ΔΣ ADC. The SBB converts acceleration to ratiometric voltage. The ratiometric output of the SBB is converted to the digital domain by the ADC. In order to achieve high resolution, a micromechanical sensor element with a high quality factor, Q, is utilised. The AC force feedback is used for damping the high Q to get a low settling time. The sensor interface is fabricated in a standard 0.35 μm CMOS process. The fabricated chip has an area of 6.66 mm2 and consumes 1 mA at a nominal supply voltage of 3.6 V. The sensor has a maximum DC nonlinearity of 1.3% over the commercial temperature range with an input range of ±1.15 g. The noise floor of the sensor is around 2 μg/√{Hz} and the signal bandwidth is 200 Hz. The bias instability is 13 μ g and the sensor gain variation is less than 5% in the 3-3.6 V supply range.

Linearity study of a self-balancing capacitive half-bridge sensor interface

This paper investigates the sources of non-linearity of a self-balancing capacitive half-bridge sensor interface. It has been shown that the linearity of the interface output with respect to input acceleration is infinity at DC input signals when half-bridge sensor element is assumed as parallel plate capacitor pair. The linearity degrades as the input signal frequency gets higher. The source of the non-linearity is found out to be the phase difference between senor sensor element displacement and the interface output voltage. The analytical expression for the HD3 of the interface is derived. It has been seen that to increase the linearity of the interface, the phase difference can be decreased by increasing the cut-off frequency of the interface loop.

CMOS temperature sensor using periodic averaging for error reduction

A fully integrated temperature sensor is implemented in a 0.35 mum CMOS technology. Sensor can measure the temperature with maximum inaccuracy of plusmn0.56degC (3sigma) over temperature range of -40degC to +85degC. Parasitic substrate pnp transistors are used for temperature sensing. Dynamic element matching (DEM) technique is used to reduce the effect of matching errors of components. An on-chip clock source, control logic, low-pass filter and an output buffer are added to the PTAT sensor core. Further spread of components is decreased by using one point gain calibration at package level. The total power consumption of the sensor is 374 muW and the active chip area is 0.64 mm2.

A 2µA temperature compensated mems-based real time clock with ±4 ppm timekeeping accuracy

This paper presents a MEMS-based real time clock with a temperature compensation system. The implemented circuit achieves a timekeeping accuracy of ±4 ppm over -40 °C... 85 °C temperature range. It is built using a 27 kHz silicon resonator, differential PTAT temperature sensor with a 2^nd order ΣΔADC, and a DSP block for temperature frequency compensation. The circuit is powered by a 1.8V supply and draws 2 μA current. The system has been implemented using a 0.18 μm CMOS process.

A temperature sensor with 3σ inaccuracy of +0.5/-0.75 °C and energy per conversion of 0.65 μJ using a 0.18 μm CMOS technology

We present an integrated temperature sensor, which utilises bipolar transistors present in a 0.18pm CMOS process. A bipolar transistor is biased with two different current densities consecutively to have a voltage proportional to absolute temperature (PTAT). Two such bipolars are used to achieve a differential signal. The differential PTAT signal is fed to an incremental ΔΣ ADC to have temperature information in digital domain, which is then processed with an on-chip DSP block. The whole sensor can be put into power down mode after a conversion is done. The sensor operates in the temperature range from -40 °C to +85 °C. The energy per conversion is 0.65 μJ when the sensor output rate is at 3 conversions/s. The inaccuracy of the sensor is +0.5/-0.75 °C (3σ) after three point fitting.

A chopper stabilized low-power differential ΔΣ ADC

This paper presents a differential SC second-order single-bit ΔΣ analog-to-digital converter (ADC). The converter has nominal conversion rate of 100 kS/s with OSR of 1000. Differential converter topology is used. This leads to lower second order harmonic and lower offset voltage compared to single ended topology. Together with SC implementation, the differential converter also makes it possible to use high impedance common mode reference voltages for low power operation. Chopper stabilization has been used to decrease offset and low frequency noise. The converter is designed and will be implemented in a 0.35 µm CMOS process with a total active area of 0.24 mm2. Typically, it consumes 60 µA from a 3.3 V supply.