Ao Guo

Two-bit memory devices based on single-wall carbon nanotubes: demonstration and mechanism

Two-bit memory devices of SWNTs, based on the hysteresis effect, have been demonstrated for the first time. The pertinent memory behaviours seem to originate from the capacitive effect due to polarization of molecules, especially the surface-bound water molecules on SiO2 in close proximity to carbon nanotubes. Our investigations are intimately linked with ultrahigh-density memory applications, and possibly go a long way in broadening the memory applications of SWNTs, for example from nonvolatile to volatile cells.

VDNROM: A Novel Four-Bits-Per-Cell Vertical Channel Dual-Nitride-Trapping-Layer ROM for High Density Flash Memory Applications

A novel vertical channel nonvolatile memory cell with oxide-nitride-oxide-nitride-oxide (ONONO, dual nitride trapping layers) dielectrics stack is proposed and experimentally demonstrated for the first time. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the gate length scaling, and can have high capability of cell area shrinking. The fabrication process of this VDNROM device is basically compatible with planar CMOS technology. The VDNROM cell can be programmed and erased by the hot carrier injection to the localized trapping dual-nitride-layers, so it can achieve a four physical bits storage capability each cell. The reliability behaviors including the cycling endurance and the bake retention at 150degC have also been investigated and show the acceptable characteristics. The experiment results verify the VDNROM cell as a good candidate for high-density applications

Sub-50-nm Asymmetric Graded Low Doped Drain (AGLDD) Vertical Channel nMOSFET

40-nm and 32-nm channel length vertical nMOSFETs with an asymmetric graded low doped drain (AGLDD) structure (the LDD region only on the drain side) were experimentally demonstrated. Due to remarkably reduced peak electric field near the drain junction compared with conventional LDD structure, the vertical AGLDD structure can reduce the off-state leakage current and suppress the short channel effects dramatically. The fabricated device with 32-nm channel length, 4.0-nm gate oxide thickness still shows excellent short channel performance as the off-state leakage current (Ioff) and the ratio of the on-state driving current (Ion) to Ioffare 3.7 X 10-11μA/μm and 2.1 X 106, respectively.

Fabrication of silver nanowires in situ in Si chip based on a novel electrochemical method

In this paper, we report a novel electrochemical deposition (ECD) method to fabricate silver nanoscale wires and dendrites. We carry out the electrochemical deposition (ECD) process on a small piece of Si wafer. On its surface, there are micro-scale predefined silver electrodes. We use organic solution (N,N-dimethylformamide (DMF)) instead of metal salt solution as the electrolyte. Usually the fractal structures can be formed in the electrochemical deposition (ECD) process. When an external resistor is introduced in the ECD circuit, instead of fractal structures, silver nanoscale wires and dendrites can be obtained between two electrodes in situ in the Si chip. The diameters of the silver nanowires are about 40-200 nm and the electric properties of the silver nanowire with a diameter about 100 nm have been measured. We have proposed a possible formation mechanism for these silver nanoscale wires and dendrites.

Fabrication of 32 nm Vertical nMOSFETs with Asymmetric Graded Lightly Doped Drain Structure

The 32 nm channel length vertical negative metal-oxide semiconductor field-effect transistors (nMOSFETs) with asymmetric graded lightly doped drain (AGLDD) structure were experimentally demonstrated. Compared with the conventional LDD structure, due to the reduced peak electric field near the drain junction and the increased potential barrier of the channel in the off state, the vertical AGLDD structure can reduce the off-state leakage current and suppress the short-channel effects dramatically. The fabricated 32 nm AGLDD device with 4.0 nm gate oxide still shows excellent short-channel performance. The off-state leakage current (I off ) and the ratio of on current (I on ) to off-current I off are 3.7 X 10 -11 A/μm and 2.1 X 10 6 , respectively.

Ambipolar Transport Behaviors in Fullerene Peapod Transistors

The electrical transport properties of C70 and C60 fullerene peapods are investigated. We report the fabrications and performances of field-effect transistors (FETs) based on C70 and C60 fullerene peapods. A large percentage of the fullerene peapod-FETs we fabricated exhibit ambipolar characteristics with high Ion/Ioff ratio at room temperature in air. The origin of ambipolar behavior is qualitatively discussed.

Field-effect transistors based on single-wall carbon nanotubes bundles

The electric transport properties of single-walled carbon nanotubes (SWNT) bundles array have been measured. We report the fabrications and performances of nanoscale field-effect transistors (FET) based on SWNT bundles array. In addition to p-type FET, we present a new technique by which ambipolar FETs can be fabricated. The I/sub on// I/sub off/ ratio of ambipolar FETs approaches 5 orders of magnitude. The reasons for ambipolar character are also qualitatively discussed. Both p-type and ambipolar FETs exhibit hysteresis in their electrical characteristics.

Carbon nanotube FETs decorated by gold nanoparticles: Electrical properties and mechanism

The electrical transport behavior of carbon nanotube field-effect transistors (CNT-FETs) decorated with gold nanoparticles (NPs) has been investigated. After decoration with Au NPs, the Ion/Ioff ratios of nanotube FETs decrease and some of the p-type devices even change into metallic ones. The Au NPs decrease the contact resistances between the CNTs and metal electrodes, and accordingly increase the on-state electric currents of the CNT-FETs. The possible mechanisms for the effects of NPs on electrical transport properties of the CNTs have been analyzed qualitatively. Our investigations are closely linked with some promising applications of carbon nanotube hybrid materials in nanoelectronics.

Dendritic Gold Nanostructures: Fabrication and Potential Application in Nanoelectronics

Using N, N-dimethylformamide (DMF) as electrolyte and applying a DC voltage between a pair of Au/Ti electrodes, well-defined dendritic gold nanostructures could be prepared near the surface of cathode. These nanostructures were composed of gold nanocrystals with average diameter about 10-20 nm. The configurations of the dendritic gold nanostructures resemble the diffusionlimited-aggregation (DLA) patterns. From electric measurements, the authors find that these novel dendritic nanostructures may have potential applications in nanoelectrics

Gate-controlled rectifying behavior in C 70 @SWNTs networks

We observed gate-controlled current rectification in C 70 @SWNTs networks. The electrical transport characterization can be fitted well with the conventional Schottky diode model. The origin of the rectifying behavior in peapod networks device is also qualitatively discussed. This paper also demonstrates a strategy for diode fabrication based on peapod networks and selective electrical breakdown procedure.