Falong Zhou

Program/erase injection current characteristics of a low-voltage low-power NROM using high-K materials as the tunnel dielectric

The program and erase injection current characteristics of a NROM with SiO2, HfO2, LaAlO3 and Al2O3 as the tunnel dielectric, respectively, are studied in this paper. Due to the lower electron and hole energy barriers introduced by LaAlO3, both the program and erase injection current densities of the NROM using LaAlO3 as the tunnel dielectric are increased dramatically. The injection efficiency is also improved significantly, which indicates that the introduction of LaAlO3 can lower the operation voltage of NROM cells. We show that the bit line voltage can be reduced to 3 V for both program and erase operations of NROM cells with LaAlO3 of 5 nm and 8 nm equivalent oxide thickness (EOT). This can greatly reduce the additional circuits to generate high voltages in a nonvolatile memory chip, meanwhile maintaining sufficient program/erase (P/E) performance and reliability. Our study also shows that the drain disturb is alleviated during programming and erasing the NROM cell with the LaAlO3 tunnel dielectric due to the lower operating voltages (VBL = 3 V). Hence a low-voltage low-power NROM flash memory device operation can be achieved by using LaAlO3 as the tunnel dielectric, due to the enhancement of the P/E injection current.

Novel vertical channel double gate structures for high density and low power flash memory applications

The flash memory technology meets physical and technical obstacles in further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell benefits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications.

A Novel Dual-Doping Floating-Gate (DDFG) Flash Memory Featuring Low Power and High Reliability Application

In this letter, a novel Flash memory cell structure using dual doping polysilicon (p-n-p) as the floating gate, which can improve the cell performance and reliability, is proposed. Except for an additional large-angle tilted implantation, the fabrication technology is essentially compatible with standard CMOS technology. Measured results show that the new Flash cell with p-n-p-type floating gate can achieve higher programming speed, lower power, comparable erasing performance, and better data retention characteristics in comparison with conventional n-type floating-gate structure.

VDNROM: A Novel Four-Bits-Per-Cell Vertical Channel Dual-Nitride-Trapping-Layer ROM for High Density Flash Memory Applications

A novel vertical channel nonvolatile memory cell with oxide-nitride-oxide-nitride-oxide (ONONO, dual nitride trapping layers) dielectrics stack is proposed and experimentally demonstrated for the first time. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the gate length scaling, and can have high capability of cell area shrinking. The fabrication process of this VDNROM device is basically compatible with planar CMOS technology. The VDNROM cell can be programmed and erased by the hot carrier injection to the localized trapping dual-nitride-layers, so it can achieve a four physical bits storage capability each cell. The reliability behaviors including the cycling endurance and the bake retention at 150degC have also been investigated and show the acceptable characteristics. The experiment results verify the VDNROM cell as a good candidate for high-density applications

Novel silicon-based flash cell structures for low power and high density memory applications

Scaling down of conventional flash memory technology faces difficult technical challenges and some physical limitations. Novel silicon-based flash cell structures were presented in this paper as possible solutions. A novel cell structure using dual doping polysilicon (PNP) as the floating gate is proposed and experimentally exhibit higher programming speed and better data retention characteristics in comparison with conventional n-type floating-gate structure. To further enhance storage density and relax the stringent requirements of scaling, a novel vertical channel dual-nitride-trapping-layer ROM (VDNROM) as a kind of SONOS flash is proposed and experimentally demonstrated. Compared with conventional planar NROM cell, VDNROM structure can have high capability of cell area shrinking and achieve four-physical-bit per cell storage capability. The fabrication technologies of the two novel devices are fundamentally compatible with standard CMOS process

Sub-50-nm Asymmetric Graded Low Doped Drain (AGLDD) Vertical Channel nMOSFET

40-nm and 32-nm channel length vertical nMOSFETs with an asymmetric graded low doped drain (AGLDD) structure (the LDD region only on the drain side) were experimentally demonstrated. Due to remarkably reduced peak electric field near the drain junction compared with conventional LDD structure, the vertical AGLDD structure can reduce the off-state leakage current and suppress the short channel effects dramatically. The fabricated device with 32-nm channel length, 4.0-nm gate oxide thickness still shows excellent short channel performance as the off-state leakage current (Ioff) and the ratio of the on-state driving current (Ion) to Ioffare 3.7 X 10-11μA/μm and 2.1 X 106, respectively.

Fabrication of 32 nm Vertical nMOSFETs with Asymmetric Graded Lightly Doped Drain Structure

The 32 nm channel length vertical negative metal-oxide semiconductor field-effect transistors (nMOSFETs) with asymmetric graded lightly doped drain (AGLDD) structure were experimentally demonstrated. Compared with the conventional LDD structure, due to the reduced peak electric field near the drain junction and the increased potential barrier of the channel in the off state, the vertical AGLDD structure can reduce the off-state leakage current and suppress the short-channel effects dramatically. The fabricated 32 nm AGLDD device with 4.0 nm gate oxide still shows excellent short-channel performance. The off-state leakage current (I off ) and the ratio of on current (I on ) to off-current I off are 3.7 X 10 -11 A/μm and 2.1 X 10 6 , respectively.

Corner effects in vertical MOSFETs

Two kinds of corner effects existing in vertical channel gate-all-around (GAA) MOSFETs have been investigated via three-dimensional (3D) and two-dimensional (2D) simulations. Through comparison between the gate-all-around (GAA) and double-gate (DG) vertical transistors, it is found that the kind of corner effect caused by conterminous gate plays contrary roles in the GAA vertical transistors. It can suppress the leakage current at low channel doping while enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the terminal of the channel, shows that D-top structure (drain on the lop of device pillar) of vertical transistor has much lower leakage current and better DIBL effect immunity than S-top structure (source on the top of device pillar).

A novel asymmetric graded low doped drain (AGLDD) vertical channel nMOSFET with sidewall masked (SWAM) LOCOS isolation

Vertical channel nMOSFET with asymmetric graded low doped drain (AGLDD) structure and sidewall masked (SWAM) LOCOS isolation process is first investigated and experimentally demonstrated. The AGLDD structure, which is formed by conventional ion implantation and impurity diffusion, is adopted to suppress short channel effects and hot carrier effect. The SWAM LOCOS isolation is used to eliminate the parasitic polysilicon sidewall gate capacitances around the active region edge. The fabrication process of this device is compatible with planar CMOS technology. The transistors show veiy good immunity of short channel effects in DC characteristics.