Apratim Roy

Low cost computer based heart rate monitoring system using fingertip and microphone port

Heart rate of a human body can be measured considering the change of blood volume in fingertip using microcontroller based methods. In this paper, a low cost and portable method is proposed and implemented to measure heart rate from fingertip using the microphone port of a computer. The method detects the volume change of blood by an optical sensor based on infrared technology. The noisy output signal from the sensor is stripped out of unwanted components with the help of a hardware level active low pass filter. After interfacing through the microphone port, this signal is processed at software level to measure and monitor real time heart rate. The accuracy, noise suppression, and cost effectiveness of this method make it a suitable candidate for a low cost computer based heart monitoring system which can study and detect heart diseases like sleep arrhythmia.

Design of a wideband delay element for transmitted reference UWB receivers

The transmitted reference ultra-wideband (TR-UWB) scheme has generated considerable interest in the field of UWB radio and on-chip wireless interconnect systems. This paper presents a wideband delay element (WBDE) which is a major design concern for TR-UWB transceivers and introduces a novel WBDE architecture that eliminates the need for dual bipolar power supplies. A very wide range of delays of monotonic nature (100–1000ps) can be achieved by varying the dimensions of the transistors, the power supply voltage, the shunt capacitances and the number of stages in the delay chain. The WBDE, designed using IBM® 90nm CMOS technology, would make the circuit implementation of TR-UWB schemes realizable.

A simple high data rate UWB OOK pulse generator with transmitted reference for on-chip wireless interconnects

In this paper, a CMOS ultra-wideband (UWB) pulse generator is designed in IBM 90 nm technology for on-chip wireless interconnect applications. A UWB pulse is generated using the triangular pulse generation technique. The output pulse is OOK modulated according to data and each data bit is preceded by a reference pulse. A maximum data rate of 2.5 Gb/s with transmitted reference is achieved when the pulse repetition rate of the input clock is 5 GHz. The pulse width is about 60 ps and the peak-to-peak amplitude is 502 mV with −3 dB bandwidth of 20 GHz from 15 to 35 GHz. The pulse generator dissipates no static current with dynamic energy consumption of only 1.42 pJ per pulse from 1.2 V supply. High transmission rate and ultra low power consumption make this simple circuit attractive for on-chip wireless interconnects.

A window detection technique with adjustable threshold for transmitted reference receivers

This paper presents a threshold decision circuit with an adjustable detection window designed in a 90-nm IBM CMOS technology. Together with an RF mixer, the decision Section realizes the circuit implementation of the back-end of a transmitted reference ultra wideband receiver, which is yet to be reported in literature. The proposed circuit is built on a differential amplifier core and avoids the use of integrator and sampling blocks, which reduces the device burden necessary for the architecture. Moreover, the detection window threshold of the design can be regulated by three independent factors defined by the circuit elements. The circuit is tested at an input data rate of 0.1∼2.0 Gbps and the core decision section consumes 9.14 mW from a 1.2-V bias supply (with a maximum capacity/Pdc ratio of 218.8 GHz/W). When compared against other reported decision blocks, the proposed detection circuit shows improved performance in terms of capacity and power requirement.

Voltage lowering and gain control techniques for a single-supply-driven 0.7 V amplifier

A CMOS amplifier architecture is presented with a voltage lowering technique so that it can be driven from a single 0.7 V bias supply. The topology does not need scaled gate voltages (or additional bias circuits) and uses branching of its bias path to reduce power requirement. A three-stage cascaded structure is adopted for high gain with the output common-drain block realizing a gain control mechanism. The technique achieves 6 dB gain regulation (with a control voltage) at the expense of small additional power (1.27 mW). A K-band architecture is simulated with a 90-nm CMOS process to verify the proposed mechanisms. The low-power (7.37 mW) unregulated front-end achieves 27 dB gain with a noise figure range of 2.99–3.06 dB within the 20.5–22.2 GHz bandwidth. Port reflection loss figures ( and ) are analysed to be −8 dB and −11 dB. The circuit has an area requirement of 0.62 mm2 and performs better in terms of power supply requirement and potential packaging cost when compared with simulated results of published millimetre-wave amplifiers.

Common-rail powered reliability improving technique for single-supply complementary metal oxide semiconductor amplifiers

This paper presents a low-power technique to improve reliability of complementary metal oxide semiconductor (CMOS) amplifiers using a shared bias network for input gate and substrate of transistors. The circuit [named reliability improving circuit (RIC)] significantly reduces discrepancy in amplifier gain (S 21, voltage gain), noise figure (NF/NFmin) and output reflection-loss (ORL) parameters resulting from variation in threshold voltage, feature-width, device speed and supply rail. It performs well on both typical- (1.2 V) and low-voltage (0.7 V) platforms of a 90 nm CMOS technology and is able to maintain its consistency within a wide frequency coverage (10–30 GHz) for three different architectures (cascode, low-voltage cascode and common-source). This allows the RIC incorporated front-end to satisfy a broad range of gain, isolation, linearity and NF requirements. The schemes biasing arrangement is powered from amplifier rails which permit the overall circuit to be driven from a single main supply. Analysis and simulation results demonstrate the technique improving consistency of figures of merit considerably against different aspects of process/system variation without significant degradation of radio frequency performance.

A passive-matched 22 GHz 2.6-dB-NF CMOS front-end with a 70-800 ps delay block

This paper presents a power-efficient RF differential receiver front-end supporting transmitted-reference (TR) communication in a 90 nm CMOS technology. Particularly, it addresses the issues of designing the frontend amplifier with low-noise and passive matching circuits on a silicon process and integrating a low-power delay unit in the front-end with wideband characteristics. The proposed architecture includes a differential high simulated gain (11 dB) amplifier which is centered at 21.6 GHz (in the K-Band) with a 6.2 GHz bandwidth (18.1~24.3 GHz). The input and output reflection parameters have centered values around -26 and -18 dB, respectively. With noise matching, the amplifier achieves 2.6~2.9 dB bandwidth noise-figure and 2 dBm input power limit for linear coverage. To interface the amplifier with a following RF mixer, a submicron delay-block (DB) is proposed with provision of adjusting number of stages in the delay chain. The branched DB architecture achieves monotonic delays covering a range of 70-800 ps (including group-dispersion). Tweaking of delay is possible through four design parameters and the set-up is analyzed by extending the number of cascaded stages up to eight. Driven from a 1.2 V supply, the amplifier and the DB consume 13.9 and 8.52- 10.61 mW power, respectively, and realize the circuits for the TR front-end. When compared with simulated results of reported CMOS receivers, the proposed design delivers higher performance in terms of a microwave figure-of-merit.

Optimization of building blocks for multi-stage 17–44 dB 6.1–9.6 mW 90-nm K-band front-ends

In this article, five two-stage ∼6-mW and four three-stage ∼9-mW matched amplifier architectures are proposed to establish optimization procedure and quantify relative merits of cascode (CC), common-gate (CG), and commonsource (CS) building blocks for low-voltage low-power multi-stage front-ends. The circuits are simulated with a 90-nm CMOS technology including modeling of layout parasites. Integrated bias trees and passive port matching networks are incorporated in the K-band designs. In the face of process mismatch, variability in noise and gain figures remains <0.39 dB and <7.1 dB from the design values. The five combinations of building blocks in twostage low-power (6.1–6.6 mW) amplifiers achieve linearity (IIP3) in the range of −5.2∼–13.5 dBm, good reverse isolation (better than −26 dB), 2.89–3.82 dB noise penalties, and 17.2–25.5 dB peak forward gain. In case of threestage front-ends built with CS, CC, and CG blocks (power rating 9.2–9.6 mW), forward gain and optimized noise figures are found as >33 dB and <3.26 dB, respectively. They achieve −2.5∼18.3 dBm IIP3, <−39 dB reverse isolation, and <−17 dB minimum IRL. The results are compared with reported simulated findings on CMOS multistage amplifiers to highlight their relative advantages in terms of power requirement and decibel(gain)-per-watt.

Parasite sensitive analysis for a Ka-band low-power (7.1mW) low-NF wideband amplifier

In this paper, we present a Ka-band (27GHz), lowpower (7.1mW), low-noise (3.5dB) amplifier built on a 1.2-V CMOS process. New impedance and noise matching techniques are introduced to the proposed architecture through reactive inter-stage gain boosting and coupling of input matching inductors. On a platform of 0.09-μm IBM CMOS technology, extensive modeling of layout parasites and sensitivity analysis (accounting for process mismatch) are performed to ensure a reliable RF analysis. The single-stage Ka-band amplifier achieves a peak S21 of 11.3dB near 27GHz, drawing a bias current of 5.964mA from the 1.2V rail. Minimum port-reflection figures (S11 and S22) for the amplifier are -15dB and -39dB, respectively, whereas the linear range of input power (indicated by IIP3) has a maximum limit of -0.5dbm. The circuit achieves better performance in terms of bandwidth, port matching and power demand when compared with simulated results of published millimeter-wave CMOS amplifiers.

A 1.2-V 0.09-µm high-gain buffered amplifier for 14.2-GHz satellite applications

Employing a 90-nm CMOS process, this article presents a high-gain, low-power (9.2 mW), highly-linearized (IIP3: 8.5 dBm), buffered amplifier for satellite applications near the lower edge of Ku-band (14.2 GHz). Over the frequencyband of interest (13.2-15.4 GHz), the amplifier achieves low noise contribution (<;3.41 dB) and excellent port-matching (<;-10 dB) simultaneously. With an effective 3-dB bandwidth of 2.2 GHz, the circuit demonstrates a small-signal forward gain of 24 dB and a noise figure (NF) of 3.25 dB at 14.2 GHz while maintaining a minimum input return-loss of -35 dB. Effect of impedance mismatch and process parasites are included in the design to facilitate a layout-sensitive RF analysis. When compared with simulated results of published amplifiers, the proposed design fares better in terms of linearity, forward gain and watt-per-decibel requirements.