S. M. Shahriar Rashid

Design of a wideband delay element for transmitted reference UWB receivers

The transmitted reference ultra-wideband (TR-UWB) scheme has generated considerable interest in the field of UWB radio and on-chip wireless interconnect systems. This paper presents a wideband delay element (WBDE) which is a major design concern for TR-UWB transceivers and introduces a novel WBDE architecture that eliminates the need for dual bipolar power supplies. A very wide range of delays of monotonic nature (100–1000ps) can be achieved by varying the dimensions of the transistors, the power supply voltage, the shunt capacitances and the number of stages in the delay chain. The WBDE, designed using IBM® 90nm CMOS technology, would make the circuit implementation of TR-UWB schemes realizable.

A simple high data rate UWB OOK pulse generator with transmitted reference for on-chip wireless interconnects

In this paper, a CMOS ultra-wideband (UWB) pulse generator is designed in IBM 90 nm technology for on-chip wireless interconnect applications. A UWB pulse is generated using the triangular pulse generation technique. The output pulse is OOK modulated according to data and each data bit is preceded by a reference pulse. A maximum data rate of 2.5 Gb/s with transmitted reference is achieved when the pulse repetition rate of the input clock is 5 GHz. The pulse width is about 60 ps and the peak-to-peak amplitude is 502 mV with −3 dB bandwidth of 20 GHz from 15 to 35 GHz. The pulse generator dissipates no static current with dynamic energy consumption of only 1.42 pJ per pulse from 1.2 V supply. High transmission rate and ultra low power consumption make this simple circuit attractive for on-chip wireless interconnects.

A 200PS differential CMOS delay element for 10 GHz ultra wideband wireless receivers

Design of a novel selective band delay element and its performance gain over nominal low pass LC ladder based delay element is demonstrated. The delay element uses three 2nd order all pass filter as its core element and achieves a delay of 200 ± 10 ps within 6.8 GHz to 12.9 GHz range. The circuit is implemented using 130 nm RF CMOS technology. Total area of the circuit is 0.88mm × 0.86mm without bondpad and 0.88mm × 1.06mm with bondpad. The circuit uses only passive elements, thus there is no static power consumption. Maximum dynamic power consumption is found to be 6μW.

Design of a double balanced square law CMOS up-conversion mixer with improved input isolation technique for high frequency applications

In this paper, a square law CMOS double balanced mixer is designed in IBM 90nm technology with improved input isolation technique for high frequency applications. Responses of the circuit is demonstrated when a 1GHz signal is up converted by a 19GHz carrier. Conversion gain (S21) of the mixer is 11.4dB with 4.5GHz Bandwidth (17.3GHz to 21.8GHz) and the input-output matching parameters (S11 and S22) are −18dB and −18.8dB respectively. Noise figure of the circuit is 6.1dB and the power consumption is 9.25mW, the power supply being 1.2V. It achieved an input referred 1dB compression point of −10.8dBm and the IIP3 is about 0dBm. The mixer has the flexibility of being used as a single balanced one as well. The input isolation is improved and is better than −15dB at the input frequencies of interest, which makes this simple circuit attractive for high frequency applications. The group delay distortion was analyzed with the help of a three tone test signal and was found satisfactory.

Microprocessor Based Design of the Control Mechanism of Automatic Mail Sorting Machine

Application of modern control mechanism on mail sorting system may be an efficient approach of reducing the delays and mismanagements, experienced in our traditional postal system. In this paper, we have developed an efficient idea of control mechanism of automatic mail sorting machine (AMSM) based on microprocessor (8086). Detail description of the machine together with necessary control words and other signals are also included here.

A power efficient bandwidth regulation technique for a low-noise high-gain RF wideband amplifier

In this paper, a single-stage deep sub-micron wideband amplifier (LNA) using a reactive resonance tank and passive port-matching techniques is demonstrated operating in the microwave frequency range (K band). A novel power-efficient bandwidth (BW) regulation technique is proposed by incorporating a small impedance in the resonance tank of the amplifier configuration. It manifests a forward gain in the range of 5.9–10.7 dB covering a message bandwidth of 10.6–6.3 GHz. With regulation, input-output reflection parameters (S11, S22) and noise figure can be manipulated by −12.7 dB, −22.7 dB and 0.36 dB, respectively. Symmetric regulation is achieved for bandwidth and small signal gain with respect to moderate tank impedance (36.5% and −26.8%, respectively) but the effect on noise contribution remains relatively low (increase of 7% from a base value of 2.39 dB). The regulated architecture, when analyzed with 90 nm silicon CMOS process, supports low power (9.1 mW) on-chip communication. The circuit is tested with a number of combinations for tank (drain) impedance to verify the efficiency of the proposed technique and achieves better figures of merit when compared with published literature.

A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process

In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectre with 0.13μm CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz Bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit achieves a NF of 2.9 dB at the center frequency and consumes only 3.38 mW of power when driven from 1.2 Vpower supply. To the best of the authors’ knowledge, a single stage LNA operating at such high frequency is yet to be reported.