Sheikh Nijam Ali

RF switch-mode power amplifier with an integrated diplexer for signal reconstruction and energy recovery

A new RF switch-mode power amplifier architecture is proposed as an alternative to other switch-mode amplifier designs based on class D or class S circuits. Class D/S circuits have a number of implementation challenges including output baluns, high swing drivers, and protection diodes. In the proposed design, a single switching device is driven by a pulse train and matched to an output diplexer. The diplexer has complementary bandpass and bandstop filter characteristics where the bandpass filter is used for signal reconstruction and the bandstop filter is used to capture out-of-band energy and recycle RF power to enhance power efficiency. An experimental prototype of the driver, switch-mode amplifier and diplexer have been implemented to demonstrate the amplifier concept. A drain efficiency of 70% is measured over a frequency range of 400 MHz to 850 MHz at an output power of 10 W. Future extensions of the work will include implementations of the energy recovery circuit to recycle out-of-band RF load power.

A new high efficiency RF switch-mode power amplifier architecture for pulse encoded signals

A new architecture for RF switch-mode power amplifiers is proposed. In this design, a pulse encoded signal switches a single RF power device with a broadband output match coupled to an output diplexer. The broadband termination impedance across the device minimizes switching losses. A complementary diplexer design is used to implement a bandpass reconstruction filter required for the pulse encoded signal as well as a broadband bandstop filter to separate out-of-band spectral power from the reconstructed output signal. The bandstop filter output terminal also provides an option to enhance power efficiency by incorporating an energy recovery circuit in a feedback loop to the DC power supply. The recovery circuit has the potential to significantly boost power efficiency under back-off conditions. Simulated results are presented for a 2 GHz 25 W GaN power device. For a sigma-delta encoded pulse train, the power efficiency is 65.5% at an output power of 43.7 dBm and for a pulse position modulated signal the power efficiency is 65.7% efficiency at an output power of 44.3 dBm.

Reconfigurable high efficiency power amplifier with tunable coupling coefficient based transformer for 5G applications

A frequency reconfigurable high efficiency power amplifier (PA) is presented for 5G applications using on-chip switchable matching networks. To cope with increased gate-drain capacitance (Cgd) in deep submicron CMOS PA design at mm-Wave frequencies, a tunable coupling-coefficient based transformer is proposed. This technique dramatically improves the neutralization of Cgd in a common-source PA while maximizing output power and efficiency. To reconfigure the PA between 24 GHz and 28 GHz, a low-loss reconfigurable matching topology is adopted using a switched substrate-shield inductor. Using the proposed techniques, a single-stage reconfigurable class-AB PA is demonstrated in 65 nm CMOS, achieving 42.6% maximum power added efficiency (PAEmax), 14.7 dBm maximum output power (Po, max) at 24 GHz and 40.1% PAEmax, 14.4 dBm Po, max at 28 GHz. The PA occupies a core area of 0.11 mm2 only.

Current reuse triple-band signal source for multi-band wireless network-on-chip

A current reuse triple-band signal generator is proposed which simultaneously generates a first, second, and third harmonic output signal from a 26.5–30.2 GHz fundamental voltage controlled oscillator (VCO). Transformer-based Gm boosting and passive 2nd harmonic extraction is proposed to achieve a good performance with exceptionally low power. A low-voltage modified Gilbert cell mixer generates the third harmonic while requiring minimal voltage overhead, facilitating an efficient current reuse topology. The fabricated signal generation circuit consumes 8 mW of power and achieves a 13% tuning range and a measured phase noise of −121 dBc/Hz at 10 MHz offset. The proposed signal source demonstrates best-in-class performance among multi-band signal sources.

A 42–46.4% PAE continuous class-F power amplifier with C gd neutralization at 26–34 GHz in 65 nm CMOS for 5G applications

This paper presents a wideband high efficiency continuous class-F (CCF) power amplifier (PA) at mm-Wave frequencies for the first time. A tuned load with a high-order harmonic resonance network is used to shape the current and voltage waveforms for the proposed CCF CMOS PA. Further, a transformer with a tunable coupling-coefficient (ktune) is incorporated in the tuned load network to address the detrimental feedback effect caused by the increased transistor gate-drain capacitance (Cgd) in deep submicron CMOS technology. This technique allows precise neutralization of Cgd, reducing undesirable influence on the tuned load, and maximizing power-efficiency and stability. The CCF PA prototype, implemented in 65 nm CMOS exhibits more than 42% power added efficiency (PAE) over 8 GHz bandwidth (26–34 GHz), while delivering saturated output power (Psat) of 14.75 dBm at 30 GHz. This design presents one of the highest reported PAEs among mm-Wave CMOS PAs, achieving 46.4% peak PAE at 29 GHz.

Reconfigurable phased-array design techniques for 5G and beyond communications

This paper presents the design of multi-band millimeter-wave (mmW) phased-array communication systems for wideband applications. A multi-band matching network (MN) design is proposed using a novel low-loss reconfigurable-inductor (RI). Furthermore, a reconfigurable-transformer (RT) is shown for an accurate neutralization of the gate-drain capacitance (Cgd), which improves the efficiency and stability of mmW power-amplifiers (PAs). The proposed reconfigurable design techniques can be used in the design of phased-array front-end circuits to maximize their power-efficiency and bandwidth (BW).