Arisa Hara

Overview: continuous evolution on double-patterning process

Double Pattering process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device, and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pith-Quadrupling (SAQP) achieved 11nm hp as introduced in last SPIE[1]. PR-core technique will be most friendly for lithographer, because its property can be recognized on lithography view point. ALD (Atomic Layer deposition) SiO2 process is the one of unique technique for multiple-patterning, and it is also useful for pitch-doubling in hole pattern [2]. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened. In this study, we would demonstrate newly developed multi-patterning techniques and optimize CD-uniformity, LWR and process latitude.

Sub-12nm optical lithography with 4x pitch division and SMO-lite

The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A “lines and cuts” approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm.[1] In previous work, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 16nm node.[2,3,4,5] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[6,7] This is significant since mask data volumes of <500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using SMO with simplified OPC in a technique called “SMOLite” beyond 16nm. The same “cut” pattern is used for each set of simulations, with “x” and “y” locations for the cuts scaled for each node. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Another approach for scaling the “cut” pattern has also been studied. This involves the use of a hole pitch division process to create a grid template combined with a relatively large “selection” pattern to create cuts at the desired grid locations. Experimental demonstration of the cut approach using SMO-Lite and a grid template will be presented. Wafer results have been obtained at a line half-pitch of 20nm, which corresponds to the gate pitch at the 10nm node.

The important challenge to extend spacer DP process towards 22nm and beyond

Double patterning processes are techniques that can be used to form etching mask patterns for 32nm node and possibly for 22nm node as well. The self-aligned spacer process has drawn much attention as an effective means of enabling the formation of repetitive patterns. The self-aligned spacer process is now being used in actual device manufacturing, but it has many process steps driving up process cost while also assuming a 1D pattern. This paper demonstrates extensions of the self-aligned spacer process by an enhanced 2D positive spacer process and a newly developed spacer DP process using a 1D negative spacer.

Sustainable scaling technique on double-patterning process

The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the self-aligned type of double patterning, such as self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP)[1], we have reported that spacer-pattern processing is more difficult than line-pattern processing since the former includes more fluctuating factors, and that improving the performance of the core pattern is essential to solving this problem. Similarly, as calls for even more improvement in line edge roughness (LER) have come to be made, we have investigated the relationship between the core pattern and LER. Thus, given the importance of finding a means of securing pattern fidelity in the core pattern to improve critical dimension uniformity (CDU) and LER, we improved resist contrast resulting in dramatically reduced LER and improved spacer CD uniformity over the wafer surface. This paper presents the results of observing pattern fidelity in the double patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity.

CD error budget analysis for self-aligned multiple patterning

EUV lithography is one of the most promising techniques for sub-20-nm half-pitch HVM devices, however it is well known that EUV lithography solutions still face significant challenges. Therefore we have focused on self-aligned double patterning (SADP), because SADP easily enables fine periodical patterning. As you know, SADP techniques have already been applied to HVM devices such as NAND Flash memory. These techniques will also be extended to DRAM and logic mass-production devices in the near future. In general, self-aligned multi-patterning consists of SADP, triple patterning (SATP), quadruple patterning (SAQP), etc. We have already introduced innovative resist core based SADP/SAQP techniques and have demonstrated results in past SPIE sessions.[1][2][3] Our proposed SiO2 spacer is directly deposited on a resist core by a low-temperature deposition process.SATP and SAQP enable further down-scaling to 10-15 nm hp from SADP levels, however the CD controllability for SATP/SAQP becomes more sensitive. In this paper, we will discuss CD error budget analysis for self-aligned multi-patterning, including a newly developed SATP scheme.

The enhanced photoresist shrink process technique toward 22nm node

In fine patterning process technology, the pattern shrink process technique is indispensable in addition to pitch shrink. Tokyo Electron has previously demonstrated the application of this technique to trench-pattern shrink for dual trench LELE, simple hole shrink for the circular pattern, and rectangle pattern shrink for cut mask of SADP+line cut. In this paper, we introduce technology that can shrink photoresist for application to a short-trench and contact hole pattern. Using chemical shrink as a reference for comparison, we report on the effectiveness of TELs original ALD SiO2 shrink process. In addition, we propose various contact pitch shrink schemes for applying double patterning technique.

Advanced self-aligned DP process development for 22-nm node and beyond

Although numerical aperture (NA) has been significantly improved to 1.35 by the introduction of water-bases immersion 193-nm exposure tools, the realistic minimum feature size is still limited to 40 nm even with the help of robust resolution enhancement techniques (RETs). Double patterning processes are techniques that can be used for fabricating etching mask patterns for 32-nm nodes and possibly for 22-nm nodes as well. Although several double patterning processes have been introduced such as LELE[1], LLE[2] and the self-aligned spacer process, LELE and LLE suffer from the need for high overlay accuracy. The self-aligned spacer process[3], meanwhile, has drawn much attention as an effective means of forming repetitive patterns easily. This paper presents results of innovative experiments on the fabrication of 22-nm node patterns by the DP spacer process.

Robust complementary technique with multiple-patterning for sub-10 nm node device

Extreme ultraviolet (EUV) lithography is the leading candidate for sub-20nm half-pitch (hp) patterning solution, but the development of a high-output light source is still in progress thereby delaying the adoption of EUV for mass production. The evolution of 193nm immersion lithography-an exposure technology currently used in the mass production of all advanced devices-must therefore be extended, and to this end, self-aligned multiple patterning (SAMP) processes have come to be used to achieve further down scaling. To date, we have demonstrated the effectiveness of self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as innovative processes and have reported on world-first scaling results at SPIE on several occasions. However, for critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for line-cutting techniques (grating and cutting). Under the theme of existing- technology extension to sub-10nm logic nodes, this paper presents the potential solutions of sub-10nm hp resolution by self-aligned octuple patterning (SAOP) and discusses the limits of shrink technology in cutting patterns.

Process variability of self-aligned multiple patterning

EUV lithography is one of the most promising techniques for sub 20nm half pitch HVM devices, however it is well known that EUV lithography solutions still face significant challenges. Therefore we have focused on 193 based self-aligned multiple patterning, because SAMP(SADP to SAQP) easily enables fine periodical patterning. As you know, these spacer based techniques have already been applied to NAND,DRAM,Logic mass productions. We have already introduced innovative resist core based SADP/SAQP techniques and have demonstrated results in past SPIE sessions.[1][2][3][4] Although SAMP technique can be easily extend to the gridded pattern for 1D layout, the resolution limit of gridded design rule will strongly depend on hole pitch shrink technique for the cut-pattern. In this paper, we will introduce GDR demonstration result of the 10nm logic node, and discuss about the process variability relevant to them.

Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond

Historically, lithographic scaling has been driven by both improvements in wavelength and numerical aperture. In the semiconductor industry, the transition to 1.35NA immersion lithography has recently been completed, and the focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleighs definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for various device layouts.