Masatoshi Yamato

Sustainable scaling technique on double-patterning process

The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the self-aligned type of double patterning, such as self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP)[1], we have reported that spacer-pattern processing is more difficult than line-pattern processing since the former includes more fluctuating factors, and that improving the performance of the core pattern is essential to solving this problem. Similarly, as calls for even more improvement in line edge roughness (LER) have come to be made, we have investigated the relationship between the core pattern and LER. Thus, given the importance of finding a means of securing pattern fidelity in the core pattern to improve critical dimension uniformity (CDU) and LER, we improved resist contrast resulting in dramatically reduced LER and improved spacer CD uniformity over the wafer surface. This paper presents the results of observing pattern fidelity in the double patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity.

Robust complementary technique with multiple-patterning for sub-10 nm node device

Extreme ultraviolet (EUV) lithography is the leading candidate for sub-20nm half-pitch (hp) patterning solution, but the development of a high-output light source is still in progress thereby delaying the adoption of EUV for mass production. The evolution of 193nm immersion lithography-an exposure technology currently used in the mass production of all advanced devices-must therefore be extended, and to this end, self-aligned multiple patterning (SAMP) processes have come to be used to achieve further down scaling. To date, we have demonstrated the effectiveness of self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as innovative processes and have reported on world-first scaling results at SPIE on several occasions. However, for critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for line-cutting techniques (grating and cutting). Under the theme of existing- technology extension to sub-10nm logic nodes, this paper presents the potential solutions of sub-10nm hp resolution by self-aligned octuple patterning (SAOP) and discusses the limits of shrink technology in cutting patterns.

Recent progress on multiple-patterning process

The optical projection technique with evolution of Exposure wave length (λ) and Numerical Aperture (NA) has been historically driven Photolithographic scaling. Although the delay of EUV tool for HVM has been concerned, scaling is going on steadily after limitation of 193nm-immersion technique. Double patterning process has been firstly adopted in 30nm node device of memory device, and evolved step by step from SADP, SAQP to SAOP [1][2][3]. Self-Aligned Multiple-Patterning (SAMP) with 193-immersion is getting most promising technology for further downwards scaling at the present. For the extension of 193-immersion, many solutions in mask and illumination area were suggested, and these are represented by SMO (Source and Mask Optimization) and linked to “Computational lithography”. Furthermore, the change of device layout design to 1D (Single directional) layout [4] is the solution to mitigate several process issues, which are represented by process variability, pattern fidelity and Edge placement error (EPE). This paper presents the results of observing pattern fidelity in the multiple patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity in 1D layout.

Extendibility of self-aligned type multiple patterning for further scaling

Photolithography has been a driving force behind semiconductor scaling, but the technology has been at a standstill since the development of 193-nm water-based immersion lithography. As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP)[1] to pitch-quadrupling by self-aligned quadruple patterning (SAQP)[2]. We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns. While waiting for the development of extreme ultraviolet (EUV) lithography tools to be completed, it will be necessary to search out possibilities for further semiconductor scaling using the double patterning process as the mainstream technique for extending the life of 193-nm immersion lithography.

Innovative solutions on 193 immersion-based self-aligned multiple patterning

EUV lithography is one of the most promising techniques for sub-20nm half-pitch HVM devices, however it is well known that EUVL solutions still face significant challenges. Therefore we have focused on 193 immersion extension by using a self-aligned multiple patterning (SAMP), and this technique easily enables fine periodical patterning. Spacer patterning techniques have already been applied to sub-20nm hp advanced devices. In general, SAMP consists of SADP, SATP, SAQP, etc. We have already introduced about evolutional schemes and cost effective processes in past SPIE sessions.[1-12] SAQP enable further down-scaling to 10nm hp from SADP levels, however we must consider next advanced solution for sub-10nm hp resolution. In this paper, we will discuss about a possibility of 193 immersion extension using SAOP (self-aligned octuple patterning).

Noble approaches on double-patterning process toward sub-15nm

Double Patterning process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device[1], and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pitch-Quadrupling (SAQP) achieved 11nm hp as introduced in previous our study[2]. Sa-MP has been required to mitigate a process complexity and cost impact. Furthermore, Process variability, Pattern fidelity, CD metrology for sub 20nm pattern also has to be considered. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened.

Sustainability and applicability of spacer-related patterning towards 7nm node

Self-aligned multiple patterning technique has enabled the further down scaling through 193 immersion lithography extension [1-5]. In particular, focus on the logic device scaling, we have finished the verification of patterning technology of up to 10nm node [6-7], we will discuss about some patterning technologies that are required to 7nm node. For critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for pattern cutting process. In 7nm node, cutting number increase in metal or fin layer, and also pattern splitting of contact or via is complicated, so both cost reduction and process controllability including EPE are strongly required. For example, inverse hardmask scheme in metal layer can improve CD variation of the Cu wiring. Furthermore hole pattern shrink technology in contact layer, by the combination with the exposure technique which has k1 0.25 or less, can achieve both cost reduction and reducing the numbers of pitch splitting. This paper presents the possibility of immersion-based multiple patterning techniques for up to 7nm node.

Recent progress on multipatterning: approach to pattern placement correction

Multi-patterning technology using 193nm immersion lithography has been used since the 22nm logic node generation and it appears that it will continue to be used as far as the 14nm generation. At the same time, the industry trend is to simplify pattern design and reduce complexity in lithography though single directional (1D) layout[1]. On the other hand, there is increasing concern about pattern placement error in the application of this technology. This paper focuses on pattern placement variation in the process steps of pattern formation in 1D layout design, presents the results of a study on the effects of factors other than overlay accuracy on microscopic behavior, and describes techniques for improving pattern placement.

Pattern fidelity in multiple-patterning process

Pattern roughness is expected to be an important issue in semiconductor scaling going forward. We performed smoothing of ArF photoresists (PRs) by a PR hardening technique called direct current superposition (DCS) cure,1) and we showed that this technique can achieve a roughness smoothing effect for PRs having various line edge roughness (LER) conditions. Additionally, we showed that this smoothing technique has many process advantages from the viewpoint of lithography, such as an improved mask error enhancement factor (MEEF), expanded process window, and improved local critical dimension (CD) uniformity. We consider that these advantages occur because of a CD healing effect caused by linear dependence of shrink amount with line width due to the DCS cure technique.

Process requirement of self-aligned multiple patterning

EUV lithography is one of the most promising techniques for the advanced patterning, however it is well known that EUVL solutions still face significant challenges. Therefore we have focused on 193 based self-aligned multiple patterning, because SAMP(SADP to SAQP) easily enables fine periodical patterning. As you know, current EUVL cannot satisfy enough resolution for sub 10nm hp critical patterning. We have already introduced innovative 193 based SADP/SAQP techniques and have demonstrated results in past SPIE sessions.[1][2][3][4] we will recommend the dry cleaning technique for the pattern collapse issue of 2nd core formation. On the other hand, we have to assume the possibility of EUV+SADP in order to interpolate the EUV resolution limit. In this paper, we will discuss about the requirement process factors of 193+SAQP and EUV+SADP.