Masato Kushibiki

The important challenge to extend spacer DP process towards 22nm and beyond

Double patterning processes are techniques that can be used to form etching mask patterns for 32nm node and possibly for 22nm node as well. The self-aligned spacer process has drawn much attention as an effective means of enabling the formation of repetitive patterns. The self-aligned spacer process is now being used in actual device manufacturing, but it has many process steps driving up process cost while also assuming a 1D pattern. This paper demonstrates extensions of the self-aligned spacer process by an enhanced 2D positive spacer process and a newly developed spacer DP process using a 1D negative spacer.

Advanced self-aligned DP process development for 22-nm node and beyond

Although numerical aperture (NA) has been significantly improved to 1.35 by the introduction of water-bases immersion 193-nm exposure tools, the realistic minimum feature size is still limited to 40 nm even with the help of robust resolution enhancement techniques (RETs). Double patterning processes are techniques that can be used for fabricating etching mask patterns for 32-nm nodes and possibly for 22-nm nodes as well. Although several double patterning processes have been introduced such as LELE[1], LLE[2] and the self-aligned spacer process, LELE and LLE suffer from the need for high overlay accuracy. The self-aligned spacer process[3], meanwhile, has drawn much attention as an effective means of forming repetitive patterns easily. This paper presents results of innovative experiments on the fabrication of 22-nm node patterns by the DP spacer process.

LWR reduction by novel lithographic and etch techniques

The reduction of line width roughness (LWR) is a critical issue in developing resist materials for EUV lithography and LWR represents a trade-off between sensitivity and resolution. Additional post pattern processing is expected as an LWR reduction technique without impact to resolution or sensitivity. This paper reports the LWR reducing effect of a post-development resist-smoothing process. Approximately 20% improvement in LWR for ArF immersion exposed resist patterns was achieved for two types of resist and two illumination conditions. The LWR after BARC etching in which resist-smoothing was applied was decreased relative to the case in which smoothing was not applied. Resist-smoothing process also reduced LWR of an EUV exposure resist pattern by approximately 10%. These results confirm that resistsmoothing process is robust for different resists and illumination conditions.

Fabrication of 22-nm poly-silicon gate using resist shrink technology

Exposure wave length has been changing rapidly with the shrink of design rule. In 32nm node and beyond, it is predicted that keeping good resolution performance of resist pattern with small dimension and high density will be more difficult due to the drop of optical contrast in 193nm immersion lithography. EUV lithography and Double Patterning using 193nm immersion lithography are being investigated as alternative technologies, but it is currently difficult to keep enough process margins in device fabrication. Resist slimming technology by dry process and exposure process is also being investigated based on these technical backgrounds but many technical challenges have been reported. We started to develop our original resist slimming technology in track process with the aim of overcoming technical challenges and cost reduction, which is one of main challenges in double pattering. In this paper, we report the basic characteristics of our resist slimming process (controllability of CD shrink, CD uniformity within wafer, LWR, and total process margin) and also pattern transfer performance of CD and LWR after dry etching in order to apply this slimming technology to Double Pattering.

Important challenges for line-width-roughness reduction

It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary, is measured in each process step of spacer process.

Fine Trench Patterns with Double Patterning and Trench shrink Technology

As part of the trend toward finer semiconductor design rules, studies have begun in the field of semiconductor lithography technology toward the 32nm-node and 22nm-node generations. The development of various types of fine-processing technologies is underway and particular progress is being made in the development of high numerical aperture (NA) technology and extreme ultraviolet (EUV) lithography for 32nm processes and beyond. At present, however, many technical issues are still being reported. One problem of special concern relates to the forming of fine, high-density trench patterns. Here, the required process margin is difficult to achieve by existing fine-processing techniques compared to lines and space patterns, and it is predicted that this problem could be a factor in lower yields caused by pattern defects. To solve this problem, studies have begun on double patterning technology and various shrink technologies. To place the joint use of these technologies on the road toward genuine mass-production applications, it is becoming increasingly important that comprehensive efforts be made to improving the basic performance of exposure-equipment and single lithography processes, to improving the alignment accuracy in double patterning, and to extract problem points in critical-dimension (CD) and defect control toward an exposure-equipment/ coater/developer cluster tool. In the face of these technical issues, NIKON Corporation and Tokyo Electron Ltd.(TEL) have joined forces to study technology for forming fine, high-density trench patterns and have successfully developed a fine, high-density trench-pattern formation process through the joint use of double patterning technology and original Chemical Vapor Deposition (CVD)-shrink technology. This paper reports on the results of a comprehensive process evaluation of double patterning technology using lithography clusters, CVD tools and etching tools.

Fabrication of 32-nm contact/via hole by photolithographic-friendly method

As semiconductor design rules continue to shrink, studies have begun on the 32nm-node and 22nm-node generations in semiconductor lithography technology in conjunction with the development of various fine-processing technologies. Research has been especially active in the development of high-NA193nm immersion lithography and EUV lithography for 32nm processes and beyond, but at the present stage of development, many technical issues have been reported. For example, in the contact-hole and via-hole pattern formation process in 193nm immersion lithography, it is difficult to maintain good resolution performance and process margins compared to line and space patterns. Poor resolution and other defects in the lithography process are major factors behind reduced yields in semiconductor production lines, and to prevent such defects, studies have begun on double patterning technology and shrink technology applied after resist-hole-pattern formation. Here, however, the need for reducing production processes and production costs have become major issues. In response to these technical issues, we evaluated a variety of hole-shrink processes as candidates for a fine-hole-pattern formation technology, and as a result of this study, we succeeded in applying an original hole-shrink technology to the formation of 40nm hole patterns and beyond.

Fabrication of Silicon Pillar with 25 nm Half Pitch Using New Multiple Double Patterning Technique

For the higher-density cells of next-generation semiconductor memories, many recent studies have focused on the vertical cell structure technology, which includes various performance merits such as small cell size, high drivability, and suitability for cell-stacked-type arrays. The authors developed a new method to fabricate 25 nm half pitch dense Si pillars that would be applicable to the fabrication of vertical cell devices. Using the proposed multiple double patterning techniques, 23.6 nm diameter, 114 nm height Si cylindrical pillars with a half pitch of 25 nm were fabricated. We confirmed the uniformity in a 300 mm wafer at 30 points, and its 3σ was only 1.7 nm. Moreover, we examined the presence of pillar collapse at arbitrarily selected chip dies for confirmation. Surprisingly, there was no pillar collapse within any of the inspected areas. From these verifications, we conclude that our proposed fabrication technique for slim Si pillars is now available.

Implementation of double patterning process toward 22-nm node

In the field of photolithography, a variety of resolution enhancement techniques (RETs) are being applied under the mainstream technology of 193-mm water-based immersion lithography. The resolution performance of photoresist, however, is limited at 40 nm. Double patterning (DP) is considered to be an effective technology for overcoming this limiting resolution. Many double-patterning techniques have come to be researched such as litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and self-aligned spacer DP, but as the pattern-splitting type of double patterning requires high overlay accuracy in exposure equipment, the self-aligned type of double patterning has become the main approach. This paper introduces the research results of various double-patterning techniques toward 22nm nodes and touches upon newly developed elemental technologies for double patterning.

Precise CD control techniques for double patterning and sidewall transfer

We have successfully developed a self-limiting chemical dry etch process, associated equipment, and process flow featuring no use of plasma and no mask bending. In this process and process flow, the system performs mask trimming for critical dimension (CD) adjustments after hard-mask formation. First, the CD as defined in lithography is directly transferred by reactive ion etching (RIE) to silicon oxide film that is to become the hard mask. Next, reactive gas is deposited on the surface of the silicon oxide film at low temperatures and the reaction product is evaporated at high temperatures. With this process flow, there is no need to trim a mask made of organic materials. As a result, there is no mask bending and the amount of hard-mask trimming can be set by the amount of gas flow and pressure in the chemical dry etch process enabling detailed CD control to be performed. The proposed technology means that even higher aspect ratios in masks and finer CD control can be achieved for processes such as double patterning (DP) and sidewall transfer (SWT).