Kazuhide Hasebe

High Quality SiO2/Al2O3 Gate Stack for GaN Metal–Oxide–Semiconductor Field-Effect Transistor

High quality SiO2/Al2O3 gate stack has been demonstrated for GaN metal–oxide–semiconductor (MOS) transistor. We confirmed that Al2O3 could realize a low interface-state density between Al2O3 and GaN, however, the breakdown field was low. By incorporating the merits of both Al2O3 and SiO2, which has a high breakdown field and a large charge-to-breakdown, SiO2/Al2O3 gate stack structure has been employed in GaN MOS devices. The structure shows a low interface state density between gate insulator and GaN, a high breakdown field, and a large charge-to-breakdown. The SiO2/Al2O3 gate stack has also been applied to AlGaN/GaN hybrid MOS heterojunction field-effect transistor (HFET). The MOS-HFET shows excellent properties with the threshold voltage of 4.2 V and the maximum field-effect mobility of 192 cm2 V-1 s-1.

The important challenge to extend spacer DP process towards 22nm and beyond

Double patterning processes are techniques that can be used to form etching mask patterns for 32nm node and possibly for 22nm node as well. The self-aligned spacer process has drawn much attention as an effective means of enabling the formation of repetitive patterns. The self-aligned spacer process is now being used in actual device manufacturing, but it has many process steps driving up process cost while also assuming a 1D pattern. This paper demonstrates extensions of the self-aligned spacer process by an enhanced 2D positive spacer process and a newly developed spacer DP process using a 1D negative spacer.

Novel approaches to controlling photo-resist CD in double patterning processes

Numerical aperture (NA) has been significantly improved to 1.35 by the introduction of water-based immersion 193-nm exposure tools, but the realistic minimum feature size is still limited to 40 nm even with the help of robust resolution enhancement techniques (RETs). Double patterning processes are techniques that can be used for fabricating etching mask patterns for 32-nm nodes and possibly for 22-nm nodes as well, but the aspect ratio of such etching mask patterns have been reduced with scaling. At the same time, dramatic improvements in the etching durability of photo resist have not been made. This paper introduces a robust pattern-slimming process that maintains pattern height.

Important challenges for line-width-roughness reduction

It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary, is measured in each process step of spacer process.

Fabrication of 32-nm contact/via hole by photolithographic-friendly method

As semiconductor design rules continue to shrink, studies have begun on the 32nm-node and 22nm-node generations in semiconductor lithography technology in conjunction with the development of various fine-processing technologies. Research has been especially active in the development of high-NA193nm immersion lithography and EUV lithography for 32nm processes and beyond, but at the present stage of development, many technical issues have been reported. For example, in the contact-hole and via-hole pattern formation process in 193nm immersion lithography, it is difficult to maintain good resolution performance and process margins compared to line and space patterns. Poor resolution and other defects in the lithography process are major factors behind reduced yields in semiconductor production lines, and to prevent such defects, studies have begun on double patterning technology and shrink technology applied after resist-hole-pattern formation. Here, however, the need for reducing production processes and production costs have become major issues. In response to these technical issues, we evaluated a variety of hole-shrink processes as candidates for a fine-hole-pattern formation technology, and as a result of this study, we succeeded in applying an original hole-shrink technology to the formation of 40nm hole patterns and beyond.

Implementation of double patterning process toward 22-nm node

In the field of photolithography, a variety of resolution enhancement techniques (RETs) are being applied under the mainstream technology of 193-mm water-based immersion lithography. The resolution performance of photoresist, however, is limited at 40 nm. Double patterning (DP) is considered to be an effective technology for overcoming this limiting resolution. Many double-patterning techniques have come to be researched such as litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and self-aligned spacer DP, but as the pattern-splitting type of double patterning requires high overlay accuracy in exposure equipment, the self-aligned type of double patterning has become the main approach. This paper introduces the research results of various double-patterning techniques toward 22nm nodes and touches upon newly developed elemental technologies for double patterning.