Arkadiusz W. Luczyk

Enhanced LEON3 core for superscalar processing

Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-on-Chip (SoC) evolution. The paper presents the methodology of enhancing LEON3 processor IP core with superscalar abilities for low-power or high-performance systems. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle with only one third increase in area occupation. The Enhanced LEON3 IP core was synthesized using UMC 90 nm CMOS technology.

Power Dissipation in Basic Global Clock Distribution Networks

In the paper power dissipation and maximal frequency of basic global clock distribution networks is analyzed. Basic topologies of trees and meshes were implemented and simulated in AMS CMOS 0.35 mum technology. Also, a circuit of basic ring oscillator was designed. The comparison of power dissipation and maximal working frequency between those structures was performed.

MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio

MDCT is the basic processing component for high quality audio compression. It is also the most computationally intensive operation in the vast majority of audio compression standards. Mostly used audio standard for audio compression is still MP3. This paper presents new implementations of five MDCT / IMDCT architectures with different parallelization levels for MP3. Implementation utilize UMC 90 nm CMOS technology. Design was optimized for low power applications. Low power libraries and clock gating technique were used for power reduction. All IP cores are capable of computing forward and backward MDCT and this feature makes them universal in multimedia SoCs for accelerating the MP3 audio compression/decompression.

Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures

In the paper a local clock signal generator is presented. The structure was designed in regard to use it in GALS (globally asynchronous locally synchronous) architectures. The circuit was implemented in UMC (United Microelectronics Corporation) 90 nm CMOS technology. Performed post-layout electrical simulations shown that generated frequency can be efficiently controlled in different working conditions with relative error not greater than 13%.

Analysis of Basic Pausable Local Clock Signal Generator

In this paper local clock signal generator basing on three different ring oscillators is discussed. The structure was designed to verify possibility of local clock signal generation using basic delay stages. General simulations were performed to analyze power dissipation and stability of frequency in regard to temperature, transistor model and layout extraction parameters. All circuits were designed in standard CMOS 0.35 mum technology.

Monitoring of dynamic movements using acceleration measurements

Measuring and monitoring of dynamic movements in sport is important. Many of used methods are biased or invasive. In this paper acceleration measurements has been proposed to solve this problem. Three different dynamic movements has been measured: run, jump and punch. Presented results shows that measurements of acceleration may be used for movement parameters extraction and tiredness monitoring of a sportsman.

Various MDCT implementations in 0.35μ CMOS

MDCT is the most computationally intensive operation in most audio compression standards. The paper presents ASIC implementations of Ave 12/36-point MDCT architectures. All IP cores are capable of computing forward and backward MDCT and this makes them universal in multimedia SoCs for accelerating the MP3 compression/decompression. The main difference between the presented architectures is in their level of parallelization - from fully parallel to sequential architecture. The power consumption issues were observed with respect to different parallelization levels.

A method to manage unknown values generation and propagation during gate level simulations of multi-clock digital circuits

The paper presents a method for unknown signal values generation and propagation management during gate level digital simulations of multi-clock circuits. Unknown values occur at outputs of clock domain boundary flip-flops and latches when their timing parameters are violated by input signals and clocks. The method is based on gate level Verilog circuit model transformations. The transformation do not changes normal logic behaviour of the circuit but influences it only in case of timing violation. The source of a timing violation information for the method are Verilog macro functions used in standard cells library files to describe timing constraints of a particular flip-flop or latch model. Proposed method is general, flexible and able to cope with the challenges in the design process of digital multi-clock and asynchronous circuits posed by todays nanometer technologies.

Principal component analysis of accelerations in human dynamic movements: A sample set length effect study

Measuring, monitoring and analysis of dynamic movements in sports during a real-time competition is becoming more important than ever. Many methods used currently may only be applied in the artificial environment of a laboratory. Other methods require too much processing to be used efficiently in real-time. Interesting opportunity for these problems gives acceleration measurements and their usage during tournament or competition. The paper presents a case study of principal component analysis of tridimensional acceleration measurements in human dynamic movements. Three different types of dynamic movements have been measured: slow run, long distance run and jump. The presented results indicate the need to carefully adjust of the sample set length according to the dynamics of the movements, module sensor location and the type of performed movement.

Superscalar Move Architecture for Power-Aware Computing

Main sources of power dissipation in general-purpose superscalar microprocessors are concerned in the article. Some basic techniques of power dissipation reduction are presented. A concept of new superscalar MOVE (SMOVE) architecture based on MOVE and GALS (globally asynchronous locally synchronous) architecture is proposed.