Arman Vassighi

Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits

As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.

Thermal runaway in integrated circuits

In deep submicrometer technologies, increased standby leakage current in high-performance processors results in increased junction temperature. Elevated junction temperature causes further increase on the standby leakage current. The standby leakage current is expected to increase even more under the burn-in environment leading to still higher junction temperature and possibly the thermal runaway. In this paper, for the first time the concept of thermal runaway and the conditions that lead to thermal runaway is described. Also, the thermal management of high-performance microprocessors to avoid thermal runaway is investigated

Effect of CMOS technology scaling on thermal management during burn-in

Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss during burn-in. The authors estimate the increase in junction temperature with technology scaling. Their research shows that under normal operating conditions, the junction temperature is increasing 1.45/spl times//generation. The increase in junction temperature under the burn-in condition was found to be exponential. The range of optimal burn-in voltage and temperature is reduced significantly with technology scaling.

CMOS IC technology scaling and its impact on burn-in

This article describes how CMOS IC technology scaling impacts semiconductor burn-in and burn-in procedures. Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss of good parts during burn-in. The paper discusses the effect of junction temperature on device reliability, aging, and burn-in procedure optimization. The effect of device thermal runaway and the requirements it forces on commercial burn-in ovens, device package, and device cooling are also described.

Burn-in temperature projections for deep sub-micron technologies

Burn-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45X/generation. This paper estimates the increase in junction temperature with scaling and discusses the optimal burn-in temperature with scaling. Our research indicates that the burn-in temperature must also be reduced with technology scaling. The impact on commercial burn-in ovens is also described.

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional IDDQ testing ineffective. Since natural process variation together with low-VTH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for IDDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature IDDQ testing. We found that the conventional single threshold low temperature IDDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature DIDDQ test method. The difference between pass and fail current limits was estimated more than 200 £ for 0.13-mm CMOS technology. q 2002 Published by Elsevier Science Ltd.

Thermal runaway avoidance during burn-in

In deep sub-micron technologies, increased standby leakage current in high performance processors results in increased junction temperature. Elevated junction temperature causes further increase on the standby leakage current. The standby leakage current is expected to increase even more under the burn-in environment leading to still higher junction temperature and possibly the thermal runaway. In this paper we investigate the thermal management of high performance processors during burn-in.

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I DDQ Testing

The effectiveness of single threshold IDDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta IDDQ is identified as one alternative for deep submicron current measurements. Often delta IDDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the IDDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate IDDQ limits for normal and stressed operating conditions of 0.18 μm n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed ΔIDDQ testing is also investigated.

Thermal management of high performance microprocessors in burn-in environment

In deep sub-micron CMOS technologies, increased standby current in high performance processors results in increased junction temperature. This elevated temperature has a positive feedback on the standby current. If the temperature is not controlled, it may lead to thermal runaway. In this paper we investigate the thermal management of high performance chips in the burn-in environment.

Design optimizations for microprocessors at low temperature

We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refngeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30% of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.