Armond Hairapetian

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio

A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8/spl times/ oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm/sup 2/ chip in 0.5-/spl mu/m CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation.

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.

A fully integrated SONET OC-48 transceiver in standard CMOS

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-/spl mu/m CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.

OC-192 transmitter in standard 0.18/spl mu/m CMOS

A fully integrated SONET OC-192 transmitter IC using a standard CMOS process consists of an input data register, FIFO, CMU, and 16:1 multiplexer to give a 10Gb/s serial output. A higher FEC rate, 10.7Gb/s, is supported. This chip, using a 0.18/spl mu/m process, exceeds SONET requirements, dissipating 450mW.

OC-192 receiver in standard 0.18/spl mu/m CMOS

A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10Gb/s clock jitter is <4mUl(rms). The input sensitivity is <50mV with 870mW at 1.8V.

A 2.5MHz Output-Rate Delta-Sigma ADC with 90dB SNR and 102dB SFDR

A 16-b, 2.5MHz output-rate ADC for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator employing 4-b quantizers in all stages makes quantization noise sources negligible at 8X oversampling ratio. Data weighted averaging with bi-directional rotation eliminates tones generated by multibit DAC nonlinearity to increase SFDR. Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8mm2 chip in 0.5-um CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90dB SNR in the 1.25MHz bandwidth and 102dB SFDR with 270mW power dissipation.