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Dive into the research topics where Mario Caresosa is active.

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Featured researches published by Mario Caresosa.


IEEE Journal of Solid-state Circuits | 2002

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

Jun Cao; Michael M. Green; Afshin Momtaz; Kambiz Vakilian; David Chung; Keh-Chee Jen; Mario Caresosa; Xin Wang; Wee-Guan Tan; Yijun Cai; L. Fujimori; Armond Hairapetian

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.


IEEE Journal of Solid-state Circuits | 2001

A fully integrated SONET OC-48 transceiver in standard CMOS

Afshin Momtaz; Jun Cao; Mario Caresosa; Armond Hairapetian; David Chung; Kambiz Vakilian; Michael M. Green; Wee-Guan Tan; Keh-Chee Jen; Ichiro Fujimori; Yijun Cai

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-/spl mu/m CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.


international solid-state circuits conference | 2002

OC-192 transmitter in standard 0.18/spl mu/m CMOS

Michael M. Green; Afshin Momtaz; Kambiz Vakilian; Xin Wang; Keh-Chee Jen; David Chung; Jun Cao; Mario Caresosa; Armond Hairapetian; Ichiro Fujimori; Yijun Cai

A fully integrated SONET OC-192 transmitter IC using a standard CMOS process consists of an input data register, FIFO, CMU, and 16:1 multiplexer to give a 10Gb/s serial output. A higher FEC rate, 10.7Gb/s, is supported. This chip, using a 0.18/spl mu/m process, exceeds SONET requirements, dissipating 450mW.


IEEE Journal of Solid-state Circuits | 2007

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-

Afshin Momtaz; David Chung; Namik Kocaman; Jun Cao; Mario Caresosa; Bo Zhang; Ichiro Fujimori

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mW. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2dB. Differential group delay of 100 ps can also be tolerated


international solid-state circuits conference | 2001

\mu{\hbox {m}}

Afshin Momtaz; Jun Cao; Mario Caresosa; A. Hairapitian; David Chung; K. Vakitian; Michael M. Green; B. Tan; Keh-Chee Jen; Ichiro Fujimori; G. Gutierrez; Yijun Cai

A fully-integrated transceiver in standard 0.18 /spl mu/m CMOS exceeds all SONET OC-48 requirements. The serial interfaces are 2.488 or 2.667 Gb/s CMC and the parallel ones are 622 or 666 Mb/s LVDS. The output clock rms jitter is 1 ps and total power consumption including all the input/output interfaces is 500 mW.


international solid-state circuits conference | 2002

CMOS

Jun Cao; Afshin Momtaz; Kambiz Vakilian; Michael M. Green; David Chung; Keh-Chee Jen; Mario Caresosa; Ben Tan; Ichiro Fujimori; Armond Hairapetian

A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10Gb/s clock jitter is <4mUl(rms). The input sensitivity is <50mV with 870mW at 1.8V.


symposium on vlsi circuits | 2006

Fully-integrated SONET OC48 transceiver in standard CMOS

Afshin Momtaz; David Chung; Namik Kocaman; Mario Caresosa; Jun Cao; Bo Zhang; Ichiro Fujimori

A 10Gbps receiver, containing an adaptive equalizer, a clock and data recovery (CDR), and a demultiplexer, is implemented in 0.13 mum CMOS. By compensating for optical dispersion, this chip recovers transmitted data after 200km of single-mode fiber at BER < 10-12 . Use of analog equalizer with digital adaptation garners total power dissipation of 950mW


international solid-state circuits conference | 2011

OC-192 receiver in standard 0.18/spl mu/m CMOS

Hui Pan; Magesh Valliappan; Wei Zhang; Kambiz Vakilian; Seong-Ho Lee; Hamid Hatamkhani; Mario Caresosa; Karo Khanoyan; Haitao Tong; Duke Tran; Anthony Brewster; Ichiro Fujimori

It has been well understood that the digital clock and data recovery (CDR) architecture has many system merits over the analog counterpart for multi-Gb/s transceivers [1]. However, the applications have been limited in systems where the clock is forwarded or has small frequency offset [2, 3], due to the finite frequency and jitter tracking capability of the digitally controlled phase rotation. Recently, tracking range up to ±7800ppm has been reported [4] to extend the applications to the SATA/SAS interfaces that require 5000ppm spread spectrum clocking (SSC) to suppress electromagnetic emissions. To enable broad acceptance in high-speed applications, the digital CDRs must have much wider tracking range.


Archive | 2004

A Fully Integrated 10Gbps Receiver with Adaptive Optical Dispersion Equalizer in 0.13/spl mu/m CMOS

Afshin Momtaz; Mario Caresosa; David Chung; Davide Tonietto; Guangming Yin; Bruce J. Currivan; Thomas J. Kolze; Ichiro Fujimori


Archive | 2004

A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS

Afshin Momtaz; Mario Caresosa

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