Cedric Killian

Smart Reliable Network-on-Chip

In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and adaptive routing algorithm errors. Both presented mechanisms are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks (data bus, input port, output port) in the NoC routers, while preserving the throughput, the network load, and the data packet latency. We provide localization capacity analysis of the presented mechanisms, NoC performance evaluations, and field-programmable gate array synthesis.

Online Routing Fault Detection for Reconfigurable NoC

In this paper we present a new efficient online routing error detection approach dedicated to fault tolerant routing algorithms for the 2-D mesh reconfigurable Network-on-Chip interconnections. The main contribution is to distinguish a routing error due to switching failure from an adaptative routing decision (bypassing a faulty area or reconfigurable region in the NoC). The originality of our approach is that it can be applied to all adaptative routing based on modified turn model and well known XY algorithm, and allows the routing of messages in the networks incorporating the regions not necessarily rectangular.

Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window

Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However, overclocking, and error detection and correction capabilities of the double sampling methods are limited due to the fixed speculation window which lacks adaptability for tracking variations such as temperature. In this paper, we introduce a dynamic speculation window to be used in double sampling schemes for timing error detection and correction in pipelined logic paths. The proposed method employs online slack measurement and conventional shadow flipflop approach to adaptively overclock or underclock the design and also to detect and correct timing errors due to temperature and other variability effects. We demonstrate this method in the Xilinx Virtex VC707 FPGA for various benchmarks. We achieve a maximum of 71% overclocking with a limited area overhead of 1.9% LUTs and 1.7% flip-flops.

A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip

We present a new reliable Network-on-Chip (NoC) suitable for Dynamically Reconfigurable Multiprocessors on Chip systems. The proposed NoC is based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of the NoC. The main originality in the proposed NoC is that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in the NoC without data packet loss thanks to a self-loopback mechanism inside each router.

Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip

The current evolution of system architectures leads towards implementation of large number of processor cores into the same circuit. This evolution actually supports the performance increase and provides the capability to support the execution of very complex applications. Nevertheless, if these new architectures propose high computational performances, an important bottleneck appears for the communications between processors. Implementation of a classical electrical NoC is generally too limited for such architectures and cannot support the bandwidth required by the applications. To address this problem, Optical Network-on-Chips (ONoCs) are studied since several years. By using integrated optical technology in addition to classical technology, an ONoC can significantly increase bandwidth and decrease latency in a MPSoC based on a 3D architecture. The integration of such optical layer into a MPSoC requires to define a protocol for the communication, and in particular a protocol for the reservation of the wavelengths which ensures the communications. This paper addresses this problem and proposes a wavelength reservation protocol handled by an Optical Network Interface (ONI) Manager for reconfigurable ONoC based on shared waveguide. It allows to efficiently allocate, at runtime, the optical communication channels for a manycore architecture. The paper describes the ONI manager architecture and reservation protocol. To evaluate the performances of this interface, we have implemented it with 28nm FDSOI technology. The synthesis results demonstrate that our interface can support a high frequency of 550 MHz with 6 wavelengths managed. From these results, we can be optimistic about the scaling of the ONoC and its capacity to manage a large number of processors and more wavelengths.

Hybrid Fault Detection for Adaptive NoC

This letter presents a hybrid approach to efficiently locating data packet errors in an adaptive network-on-chips (NoC). We propose to combine offline and online concepts based on a distributed and factorized online error detection module that will enable us to perform an efficient analysis of partial and localized area networks. This combination allows for an accurate localization of fault sources (97.79% fault coverage) by using offline detection performed at suitable moments that are defined by detecting new run-time fault occurrences through online detection. The offline error detection performed during system operation is applied in one of the reconfigurable regions maintaining the run-time NoC communications. We describe the mechanisms for efficiently associating offline and online error detection, and we evaluate performance overheads in the case of permanent data packet errors. Our approach allows to maintain a high reliability impact and NoC throughput while reducing the data packet latency.

Loopback output router for reliable Network on Chip

We present a new reliable high-performance interconnection approach destined for complex System on Chip based on the network-centric approach. The originality of our approach is to avoid the lost of data packets, detect routing errors and reduce data packets latency by emptying output buffer when the neighbour router is unavailable. We present the basic concepts of the reliability communication technique and FPGA implementations.

Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC

Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale Multiprocessor System on Chip (MPSoC). ONoC outperforms classical electrical NoC in terms of throughput and latency. The medium can support multiple transactions at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM). Moreover multiple wavelengths can be used as high-bandwidth channel to reduce transmission time. However, multiple signals sharing simultaneously a waveguide can lead to inter-channel crosstalk noise. This problem impacts the Signal to Noise Ratio (SNR) of the optical signal, which leads to an increase in the Bit Error Rate (BER) at the receiver side. In this paper we first formulate the crosstalk noise and execution time models and then propose a Wavelength Allocation (WA) method in a ring-based WDM ONoC allowing to search for performance and energy trade-offs, based on the application constraints. As result, most promising WA solutions are highlighted for a defined application mapping onto 16-core WDM ONoC.

Communication Aware Design Method for Optical Network-on-Chip

Optical technology promises to solve the bottleneck communication in Multiprocessor Systems-on-Chip (MPSoCs) by integrating high speed interconnections. From the system point of view, one of the most critical problems in optical communication is channel bandwidth, strongly influencing the system performance and cost. Channel bandwidth establishes the number of waveguides and wavelengths to serve each communication request. Dynamic approaches allow to define the channel bandwidth at the runtime, which leads flexible systems but may turn their performance unpredictable. Design-time approaches appear as an attractive alternative to define the channel bandwidth for systems that require performance guarantees and simple solutions. A method for exploring the channel bandwidth design space is thus mandatory in order to identify the best communication channel size. In this work we explore the trade-off among channel bandwidth alternatives, performance, area and power. We show that the channel size has a strong impact on the system performance and cost. We employ synthetic and real application traffic which has been executed on Gem5. As a result we show that different channel bandwidth can improve the execution time of an application up to 75% while including low area and power penalties.

Reliable router for accurate online error detection in dynamic Network on Chip

This paper proposes a new reliable router allowing accurate online error detections in dynamic Network on Chip (NoC). The proposed router has the capability to detect and localize accurately inner or outer data packet errors of the router while distinguish between temporary and permanently errors. The error detection mechanisms of the proposed switches and advantages with regards to the other main already proposed router approaches are detailed while proving the feasibility and efficiency through several simulations online detection cases. Performance evaluation and FPGA implementation results are also given.