Edward Hrynkiewicz

Remarks on Parallel Bit-Byte CPU Structures of the Programmable Logic Controller

The paper presents some hardware solutions for the bit-byte CPU of a PLC, which are oriented for maximum optimisation of data exchange between the CPU processors. The optimization intends maximum utilization of the possibilities given by the two-processor architecture of the CPUs. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The optimal structure should enable the processors to work in parallel as much as possible, and minimize the situation, when one processor has to wait for the other.

Central Processing Units for PLC implementation in Virtex-4 FPGA

Abstract The paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking – control data are passed through the two flip-flop units with acknowledgement; without handshaking – control data are passed through the dual port RAM. Third unit – simple one processor – built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units.

Decomposition of the fuzzy inference system for implementation in the FPGA structure

The paper presents the design and implementation of a digital rule-relational fuzzy logic controller. Classical and decomposed logical structures of fuzzy systems are discussed. The second allows a decrease in the hardware cost of the fuzzy system and in the computing time of the final result (fuzzy or crisp), especially when referring to relational systems. The physical architecture consists of IP modules implemented in an FPGA structure. The modules can be inserted into or removed from the project to get a desirable fuzzy logic controller configuration. The fuzzy inference system implemented in FPGA can operate with a much higher performance than software implementations on standard microcontrollers.

Decomposition of Logic Functions in Reed-Muller Spectral Domain

The paper deals with the problems of logic function decomposition in Reed-Muller spectral domain. The Ashenhurst and the Curtis decompositions are considered. The decompositions are executed on positive polarization Reed-Muller spectrum of decomposed functions. The elaborated methods of decomposition are guided to implementation of logic functions in LUT based FPGA. The results are very promising.

PID Module for Reconfigurable Logic Controller

Abstract The paper presents a module of PID controller builds in FPGA structure of Reconfigurable Logic Controller. It presents algorithms used to built the controller and implementation process. Implementation process shows the ways of minimising the controller structure and increasing it performance in FPGA structures. Finally it discuses achieved result.

A FPGA-Based Bit-Word PLC CPUs Development Platform

Abstract The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.

An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions

The paper deals with the problems of input variables assigning to the free and bounded sets during logic function decomposition. The Ashenhurst decomposition is considered with respect to implementation of logic functions in LUT based FPGA. The method of finding profitable input variables partitioning is based on utilisation of Logic Differential Calculus. The elaborated method is very convenient especially if decomposition is carried out in Reed-Muller spectral domain because the Boolean differentials are easy calculated from Reed-Muller form of logic function which is simply calculated as reverse Reed-Muller transform. The obtained results are very promising.

An Idea of Event-Driven Program Tasks Execution

Abstract The paper presents modified idea of program execution in PLCs. Instead of serial cyclic execution of control program event-driven execution is proposed. Suggested approach to program execution allows for selective execution of program parts or tasks provided calculation condition for this part has changed since last time. There only these blocks from entire program are executed whose variables have changed since last calculation. Proposed method can be implemented as software modification or as hardware accelerated solution. The most important part of the idea is task or subprogram triggering condition computation. Methods of program optimization are discussed. In order to determine program blocks that require recalculation in current program scan execution specific hardware support is planned to be researched. Memory content change detection unit allows to determine changes in memory content since last program block execution.

Fast Operating Bit-Byte PLC

Abstract The paper presents a few different approaches to optimizing operation speed of Programmable Logic Controllers. First approach optimizes architecture of the bit-byte CPU, second optimizes program execution, next one data exchange between bit and byte processors and the last one optimizes input/output servicing. All of them lead to a two processors bit-byte architecture, which support of concurrent execution of bit and byte computation tasks. In such architecture the processors can operate without waiting one for the other.

On Translation of LD, IL and SFC Given According to IEC-61131 for Hardware Synthesis of Reconfigurable Logic Controller

Abstract The paper presents developed synthesis methodology of a hardware implemented reconfigurable logic controller from multiple languages incorporating ladder diagrams, instruction list and sequential functional chart according to IEC61131-3. It is focused on the originally developed a high performance computation model based on properly defined variable access. The method address synthesis process of logic and arithmetic operations. Presented approach is able to synthesize not only basic constructs of languages but also complex modules like timers and counters. The paper acquaint with the compilation of considered languages and complex modules into intermediate form suitable for logic synthesis process according to developed analysis, translation and mapping methods. The data flow graph has been chosen for intermediate representation of a program. An original enhancement of the DFG with attributed edges and specific nodes has been described. It allows for efficient representation and processing of logic and arithmetic formulas. The set of compilation algorithms that preserve effects of serial execution order and offer obtaining massively parallel processing unit are presented.