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Meeting Abstracts | 2007

Advanced Electrochemical Processes for Sub-50 nm On-chip Metallization

Rohan Akolkar; Chin-Chang Cheng; Ramanan V. Chebiam; Arnel M. Fajardo; Valery M. Dubin

Electrodeposition of copper in the presence of additives (e.g., a suppressor, an accelerator, and a leveler) is being used for the fabrication of on-chip copper interconnects. For current generation interconnects, the via and trench aspect ratios required to be filled using electroplating are accessible using conventional additives chemistries and plating conditions. For future generation sub-50 nm technology nodes, however, the via aspect ratios will be significantly higher (>10:1 in some cases due to the overhang caused by the PVD copper seed). For filling such aggressive geometries, conventional plating chemistries and approaches have, as of yet, shown little promise. In the present talk, several alternatives for addressing this issue will be outlined. These will include: (i) Development of advanced electroplating chemistries, (ii) Direct copper deposition on new liner metals (such as ruthenium), and (iii) Electroless copper plating. Decreasing feature sizes and scaling causes increase in the current density through Cu interconnects, requiring enhanced Cu electromigration resistance. Electroless Co caps will be discussed as a potential solution for improving Cu electromigration performance. Electroplating on Cu seed. Techniques for optimization of additives chemistries for sub-50 nm gap-fill will be discussed. Additives screening is performed using two techniques: (i) Linear sweep voltammetry on rotating disc electrode to characterize the additives suppression and/or interactions characteristics, and (ii) Gap-fill experiments on a patterned wafer. Correlating LSV data with SEM cross-sections provide valuable information regarding the additives chemistry, and its effect on the gap-fill. Electroplating on Ruthenium. Direct plating on new liner materials such as ruthenium is attractive since it provides reduced via/trench aspect ratios without significant seed overhang, thereby facilitating ‘defectfree’ gap-fill. In the present talk, the effects of current density, bath composition, and pretreatment on the nucleation site density of copper on ruthenium will be addressed. The influence of the terminal effect (caused by the resistive ruthenium seed) on the location-dependent nucleation density will be discussed. Electroless Cu deposition. Electroless copper provides two major advantages: (i) Improved wafer-scale uniformity (no resistive seed effects), and (ii) Extendibility of gap fill down to sub-50nm feature sizes. E-test data show comparable resistance of electroless Cu films to electroplated Cu, in addition to good gap fill on 6:1 aspect ratio features. Cu interconnects reliability. We have successfully demonstrated electroless deposition of cobalt on Cu lines with good uniformity on patterned wafers (Figure 3). The Co caps showed low leakage, improved electromigration resistance without any appreciable penalty in the Cu line resistance.


Electrochimica Acta | 2007

Electrochemical materials and processes in Si integrated circuit technology

Valery M. Dubin; Rohan Akolkar; Chin-Chang Cheng; Ramanan V. Chebiam; Arnel M. Fajardo; Florian Gstrein


Archive | 2006

High-resistivity magnetic film from nano-particle plating

Arnel M. Fajardo; Chang-min Park


Archive | 2007

SELECTIVE ALUMINUM DOPING OF COPPER INTERCONNECTS AND STRUCTURES FORMED THEREBY

Adrein R. Lavoie; Valery M. Dubin; John J. Plombon; Kari Harkonen; Arnel M. Fajardo


Archive | 2008

Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance

Kevin P. O'brien; Rohan Akolkar; Tejaswi K. Indukuri; Arnel M. Fajardo


Archive | 2006

Soft magnetic layer for on-die inductively coupled wires with high electrical resistance

Arnel M. Fajardo; Chang-min Park; Marc. C. French; Ebrahim Andideh


Archive | 2005

Catalytic nucleation monolayer for metal seed layers

Adrien R. Lavoie; Arnel M. Fajardo; Valery M. Dubin


Archive | 2006

Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures

Adrien R. Lavoie; Arnel M. Fajardo; Vijayakumar S. Ramachandrarao


Archive | 2006

Laminating magnetic materials in a semiconductor device

Arnel M. Fajardo; Ebrahim Andideh; Chang-min Park; Patrick Morrow


Archive | 2006

Transistor, method of manufacturing same, etchant for use during manufacture of same, and system containing same

Vijay Ramachandrarao; Oleg Golonzka; Arnel M. Fajardo

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