Rohan Akolkar

Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process

A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.

Advanced Electrochemical Processes for Sub-50 nm On-chip Metallization

Electrodeposition of copper in the presence of additives (e.g., a suppressor, an accelerator, and a leveler) is being used for the fabrication of on-chip copper interconnects. For current generation interconnects, the via and trench aspect ratios required to be filled using electroplating are accessible using conventional additives chemistries and plating conditions. For future generation sub-50 nm technology nodes, however, the via aspect ratios will be significantly higher (>10:1 in some cases due to the overhang caused by the PVD copper seed). For filling such aggressive geometries, conventional plating chemistries and approaches have, as of yet, shown little promise. In the present talk, several alternatives for addressing this issue will be outlined. These will include: (i) Development of advanced electroplating chemistries, (ii) Direct copper deposition on new liner metals (such as ruthenium), and (iii) Electroless copper plating. Decreasing feature sizes and scaling causes increase in the current density through Cu interconnects, requiring enhanced Cu electromigration resistance. Electroless Co caps will be discussed as a potential solution for improving Cu electromigration performance. Electroplating on Cu seed. Techniques for optimization of additives chemistries for sub-50 nm gap-fill will be discussed. Additives screening is performed using two techniques: (i) Linear sweep voltammetry on rotating disc electrode to characterize the additives suppression and/or interactions characteristics, and (ii) Gap-fill experiments on a patterned wafer. Correlating LSV data with SEM cross-sections provide valuable information regarding the additives chemistry, and its effect on the gap-fill. Electroplating on Ruthenium. Direct plating on new liner materials such as ruthenium is attractive since it provides reduced via/trench aspect ratios without significant seed overhang, thereby facilitating ‘defectfree’ gap-fill. In the present talk, the effects of current density, bath composition, and pretreatment on the nucleation site density of copper on ruthenium will be addressed. The influence of the terminal effect (caused by the resistive ruthenium seed) on the location-dependent nucleation density will be discussed. Electroless Cu deposition. Electroless copper provides two major advantages: (i) Improved wafer-scale uniformity (no resistive seed effects), and (ii) Extendibility of gap fill down to sub-50nm feature sizes. E-test data show comparable resistance of electroless Cu films to electroplated Cu, in addition to good gap fill on 6:1 aspect ratio features. Cu interconnects reliability. We have successfully demonstrated electroless deposition of cobalt on Cu lines with good uniformity on patterned wafers (Figure 3). The Co caps showed low leakage, improved electromigration resistance without any appreciable penalty in the Cu line resistance.

A Mechanistic Model for Copper Electropolishing in Phosphoric Acid

Copper electropolishing in phosphoric acid has been characterized using electroanalytical methods, primarily potential transient techniques. An uncommon voltage response, consisting of two distinct steps, was noted when the current was stepped to the limiting current. A slow (∼ 100-300 s, depending on agitation) and relatively small (∼50 mV) initial potential increase was followed by a fast (∼5 s) and large (∼1.5 V) potential rise. The latter always reached the oxygen evolution potential (∼ 1.6 V), irrespective of the process conditions. While the first, slow potential transient can be correlated in terms of a diffusion process, the second, rapid potential rise suggests the buildup of a highly resistive component, most likely a surface film. The nearly instantaneous potential relaxation upon current interruption further supports the resistive film model rather than a transport-related process. A two-stage mechanism is proposed and analytically modeled. Accordingly, the cupric ion concentration at the anode increases during the initial stage of the dissolution process due to transport limitations, until a saturation level is reached and a resistive surface film forms. During the second stage, the continuing imbalance between the rate of cupric ion formation and transport into the bulk leads to increasing film thickness and, consequently, to a rapid buildup in resistance. The model quantitatively correlates the experimentally measured transients and is consistent with all other observations relating to the copper electropolishing process.

Direct seed electroplating of copper on ruthenium liners

The ruthenium (Ru) liner based metallization scheme depends on the ability to electrodeposit Cu onto thin, resistive Ru substrates with substantially high Cu nuclei density. In the present paper, a novel electrochemical bath that utilizes Cu-complexing agents to improve the nucleation of plated Cu films on Ru is presented. Such chemistries can generate Cu nucleation density on Ru greater than 1012 nuclei/cm2, thereby enabling robust gap-fill in aggressive (CD∼30nm) dual damascene structures. Complexed-Cu plating chemistries thus provide great potential for extending Cu metallization to future technology nodes.

Novel High Molecular Weight Levelers Extending Gap Fill to Smaller Features

It has been recently demonstrated that a high molecular weight leveler can improve gap fill, in addition to minimizing the overburden (1). An analysis of this phenomenon and a quantitative model explaining the effect are presented here. The penetration of the high molecular weight leveler into the via is restricted due to its large size and slow diffusion, leading to preferential passivation of the wafer top surface. Since the leveler is a strong inhibitor, the applied current is therefore preferentially directed into the vias. Because the side walls are passivated by PEG, the majority of this current is directed to the via bottom, improving bottom-up fill. The process conditions and the distribution of features on the wafer affect this improvement. The model has been quantified using a computer implemented simulation combining empirical and analytical methods. Requirements for suitable additives for this application are specified, identifying polyethylenimine as one such additive.