Ramanan V. Chebiam

Effects of local Joule heating on the reduction of contact resistance between carbon nanotubes and metal electrodes

We report here a practical application of known local Joule heating processes to reduce the contact resistance between carbon nanotubes and metallic electrical contacts. The results presented in this study were obtained from a series of systematic Joule heating experiments on 289 single-walled carbon nanotubes (SWCNTs) and 107 multiwalled carbon nanotubes (MWCNTs). Our experimental results demonstrate that the Joule heating process decreases the contact resistances of SWCNTs and MWCNTs to 70.4% and 77.9% of their initial resistances, respectively. The I-V characteristics of metallic nanotubes become more linear and eventually become independent of the gate voltages (Vgs). For semiconducting nanotubes, the contact resistance has a similar decreasing tendency but the dependency of source-drain current (Ids) on Vgs does not change with the Joule heating process. This suggests that the reduction of the contact resistance and the decrease of the transport potential barrier are largely attributed to the thermal...

Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process

A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.

Advanced Electrochemical Processes for Sub-50 nm On-chip Metallization

Electrodeposition of copper in the presence of additives (e.g., a suppressor, an accelerator, and a leveler) is being used for the fabrication of on-chip copper interconnects. For current generation interconnects, the via and trench aspect ratios required to be filled using electroplating are accessible using conventional additives chemistries and plating conditions. For future generation sub-50 nm technology nodes, however, the via aspect ratios will be significantly higher (>10:1 in some cases due to the overhang caused by the PVD copper seed). For filling such aggressive geometries, conventional plating chemistries and approaches have, as of yet, shown little promise. In the present talk, several alternatives for addressing this issue will be outlined. These will include: (i) Development of advanced electroplating chemistries, (ii) Direct copper deposition on new liner metals (such as ruthenium), and (iii) Electroless copper plating. Decreasing feature sizes and scaling causes increase in the current density through Cu interconnects, requiring enhanced Cu electromigration resistance. Electroless Co caps will be discussed as a potential solution for improving Cu electromigration performance. Electroplating on Cu seed. Techniques for optimization of additives chemistries for sub-50 nm gap-fill will be discussed. Additives screening is performed using two techniques: (i) Linear sweep voltammetry on rotating disc electrode to characterize the additives suppression and/or interactions characteristics, and (ii) Gap-fill experiments on a patterned wafer. Correlating LSV data with SEM cross-sections provide valuable information regarding the additives chemistry, and its effect on the gap-fill. Electroplating on Ruthenium. Direct plating on new liner materials such as ruthenium is attractive since it provides reduced via/trench aspect ratios without significant seed overhang, thereby facilitating ‘defectfree’ gap-fill. In the present talk, the effects of current density, bath composition, and pretreatment on the nucleation site density of copper on ruthenium will be addressed. The influence of the terminal effect (caused by the resistive ruthenium seed) on the location-dependent nucleation density will be discussed. Electroless Cu deposition. Electroless copper provides two major advantages: (i) Improved wafer-scale uniformity (no resistive seed effects), and (ii) Extendibility of gap fill down to sub-50nm feature sizes. E-test data show comparable resistance of electroless Cu films to electroplated Cu, in addition to good gap fill on 6:1 aspect ratio features. Cu interconnects reliability. We have successfully demonstrated electroless deposition of cobalt on Cu lines with good uniformity on patterned wafers (Figure 3). The Co caps showed low leakage, improved electromigration resistance without any appreciable penalty in the Cu line resistance.

Resistance and electromigration performance of 6 nm wires

A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements showing line electrical resistance and electromigration as functions of material, conducting area, and interfaces are presented.

Simple test vehicle for metal fill and resistance of sub-8nm nanowire

Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabricated with existing silicon patterning recipes to achieve an electrical test vehicle that can test a range of metal candidates for interconnects. The vehicle is characterized using electron microscopy and electrical measurements.

Demonstration of a sidewall capacitor to evaluate dielectrics and metal barrier thin films

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.