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Dive into the research topics where Arthur D. Tuminaro is active.

Publication


Featured researches published by Arthur D. Tuminaro.


IEEE Design & Test of Computers | 2010

The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane

Rajiv V. Joshi; Anthony R. Pelella; Arthur D. Tuminaro; Yuen Chan; Rouwaida Kanj

Statistical approaches for yield estimation and robust design are vital in the current variation-dominated design era. This article presents a mixture importance sampling methodology to enable yield-driven design and extends its application beyond memories to peripheral circuits and logic blocks.


Archive | 1990

CMOS sense amplifier

Arthur D. Tuminaro; Yuen H. Chan; Philip T. Wu


Archive | 2005

Local bit select with suppression of fast read before write

Yuen H. Chan; Ryan T. Freese; Antonio R. Pelella; Arthur D. Tuminaro


european solid-state circuits conference | 2005

A 8Kb domino read SRAM with hit logic and parity checker

Antonio R. Pelella; Arthur D. Tuminaro; Ryan T. Freese; Yuen H. Chan


Archive | 2005

Global bit select circuit with dual read and write bit line pairs

Yuen H. Chan; Ryan T. Freese; Antonio R. Pelella; Arthur D. Tuminaro


Archive | 2007

Global bit line restore timing scheme and circuit

Yuen H. Chan; Ryan T. Freese; Antonio R. Pelella; Uma Srinivasan; Arthur D. Tuminaro; Jatinder K. Wadhwa


Archive | 2003

Self timed bit and read/write pulse stretchers

Rajiv V. Joshi; Arthur D. Tuminaro


Archive | 1991

Latch and data out driver for memory arrays.

William R. Dachtera; Leonard Carl Ritchie; Arthur D. Tuminaro


Archive | 2007

Global Bit Select Circuit Interface with Dual Read and Write Bit Line Pairs

Yuen H. Chan; Ryan T. Freese; Antonio R. Pelella; Arthur D. Tuminaro


Archive | 2004

Programmable sense amplifier timing generator

Yuen H. Chan; Timothy J. Charest; John R. Rawlins; Arthur D. Tuminaro; Jatinder K. Wadhwa; Otto M. Wagner

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