Antonio R. Pelella

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chips ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)

This paper will provide a case study of a particularly difficult debug problem (the Holey Shmoo problem) which developed while designing the IBM System/390 G6 637 MHz microprocessor chip. Resolution of this problem involved the use of some of todays newest DFD/DFT and diagnostics techniques. The discussion of the Holey Shmoo problem and its debug will serve to highlight and demonstrate some of these advanced techniques.

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75mum2 butted-junction split-word line 6T cell in 65nm SOI. The design features dual power supplies, unidirectional polysilicon, and hierarchical undamped bit lines for enhanced cell stability and performance

Evaluation and alleviation of SOI impacts on SRAM functionality and yield

Super fast Monte-Carlo techniques are applied to allow deeper insight to the yield of SOI domino circuit design techniques for SRAMs. For the first time, Read-before-Write in dual supply domino bit-select design is analyzed in the presence of floating body effects, hysteretic and process variations. The methodology provides greater ability to alleviate non-functionality by identifying yield-optimized operating ranges.

Design SRAMs for burn-in

SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density.<<ETX>>