Rajiv V. Joshi

Turning silicon on its edge [double gate CMOS/FinFET technology]

Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

In this paper, we propose a novel methodology for statistical SRAM design and analysis. It relies on an efficient form of importance sampling, mixture importance sampling. The method is comprehensive, computationally efficient and the results are in excellent agreement with those obtained via standard Monte Carlo techniques. All this comes at significant gains in speed and accuracy, with speedup of more than 100times compared to regular Monte Carlo. To the best of our knowledge, this is the first time such a methodology is applied to the analysis of SRAM designs

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >

The impact of gate-oxide breakdown on SRAM stability

We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 /spl mu/A at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown.

Design and CAD Challenges in sub-90nm CMOS Technologies

This paper discusses design challenges of scaled CMOS circuits insub-90nm technologies for high-performance digital applications.To continue scaling of the CMOS devices deep into sub-90nm tech-nologies,fully depleted SOI, strained-Si on SiGe, FinFETs withdouble gate, and even further, three-dimensional circuits will be uti-lizedto design high-performance circuits. We will discuss uniquedesign aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process vari-ations.As the scaling approaches various physical limits, new SOIdesign issues such as Vt modulation due to leakage, low-voltageimpact ionization, and higher V{t,lin} to maintain adequate V{t,sat},continue to surface.With an eye towards the future, design andCAD issues related to sub-65nm device structures such as doublegate FinFET will be discussed.

Carbon nanotube interconnects: implications for performance, power dissipation and thermal management

This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%

Three dimensional CMOS devices and integrated circuits

Three dimensional devices and, integrated circuits are attractive options for overcoming barriers in device and interconnect scaling, offering an opportunity to continue the CMOS performance trend. This paper reviews the process technology and associated design issues in three dimensional devices and integrated circuits.

The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate

This paper describes modeling and hardware results of how the soft-error rate (SER) of a 65-nm silicon-on-insulator SRAM memory cell changes over time, as semiconductor aging effects shift the SRAM cell behavior. This paper also describes how the SER changes in the presence of systematic and random manufacturing variation.

6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM

A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated. Measured results show an operating range of 0.4 V to 1.5 V and -25degC to 100degC, speed of 6.6+ GHz at IV, 25degC and yield of 90-100%.

A 500-MHz, 32-word/spl times/64-bit, eight-port self-resetting CMOS register file

A two-write-port, six-read-port, 32/spl times/64-bit register file has been designed for 2.5-V 0.5-/spl mu/m CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test compatible. The fabricated register file occupies an area of 1.84/spl times/1.55 mm/sup 2/, and the cell size is 21.6/spl times/30 /spl mu/m/sup 2/. The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs.