Yuen H. Chan

Design of the Power6 Microprocessor

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM

A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated. Measured results show an operating range of 0.4 V to 1.5 V and -25degC to 100degC, speed of 6.6+ GHz at IV, 25degC and yield of 90-100%.

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system

The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm design, while still fitting within the same power envelope. Despite the many difficult engineering hurdles to be overcome, the design team was able to achieve a product frequency of 5.2GHz, providing a significant performance boost for the new system.

Circuit design techniques for the high-performance CMOS IBM S/390 parallel enterprise server G4 microprocessor

This paper describes the circuit design techniques used for the IBM S/390® Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approaches reduced risk and shortened the design time. The use of timing-driven synthesis/placement methodologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits facilitated the balancing of design time and performance return. The use of robust PLL design, floorplanning, and clock distribution minimized clock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innovations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.

IBM POWER6 SRAM arrays

The IBM POWER6™ microprocessor presented new challenges to array design because of its high-frequency requirement and its use of 65-nm silicon-on-insulator (SOI) technology. Advancements in performance (2X to 3X improvement over the 90-nm generation) and design margins (cell stability, writability, and redundancy coverage) were major focus areas. Key elements of the POWER6 processor chip arrays include paradigm shifts such as thin memory cell layout, large signal read (without a sense amplifier), segmented bitline structure, unclamped column-half-select scheme, multidimensional programmable timing control, and separate elevated static random access memory (SRAM) power supply. There are two main array categories on the POWER6 microprocessor chip: core and nest. Processor core arrays use a single-port, 0.75-µm2, six-transistor (6T) cell and operate at full frequency, whereas the surrounding nest arrays use a smaller 0.65-µm2 cell that operates at half or one-quarter of the core frequency in order to achieve better density and power efficiency. The core arrays include the 96-KB instruction cache (I-cache) and the 64-KB data cache (D-cache), with associate lookup-path SRAM macros. The I-cache is a four-way set-associative, single-port design, whereas the D-cache is an eight-way design with dual read ports to handle multithreading capability. The lookup-path arrays contain content-addressable memory (CAM) and RAM macros with integrated dynamic hit logic circuitry. In the nest portion, an 8-MB level 2 (L2) D-cache and a level 3 (L3) directory (1.2 MB) make up the largest arrays. The latter macro designs use longer bitlines and orthogonal word-decode layouts to achieve high array-area efficiency.

Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.

760 MHz G6 S/390 microprocessor exploiting multiple Vt and copper interconnects

The G6 system is a sixth generation CMOS server for the S/390 line of products featuring a 12+2 SMP size and significant frequency improvements obtained through the use of low-Vt devices and copper interconnects. The microprocessor operates at 760 MHz at the fast end of the process distribution. The system ships at 637 MHz in a 12+2 chilled SMP configuration. Measured system performance on the 12 way is 1600 S/390 MIPs, providing over 50% more performance than the G5. This microprocessor uses CMOS7S technology, which has a 0.2 /spl mu/m process. The chip uses 6 levels of copper metal plus an additional layer of local interconnect on a 14.6/spl times/14.7 mm/sup 2/ die with 25M transistors (7M logic/18M array). The power supply is 1.9 V and the chip power is 33 W at 637 MHz.

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chips ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor

A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)

This paper will provide a case study of a particularly difficult debug problem (the Holey Shmoo problem) which developed while designing the IBM System/390 G6 637 MHz microprocessor chip. Resolution of this problem involved the use of some of todays newest DFD/DFT and diagnostics techniques. The discussion of the Holey Shmoo problem and its debug will serve to highlight and demonstrate some of these advanced techniques.