Arthur H. M. van Roermund

Analytical Models for the Wake-Up Receiver Power Budget for Wireless Sensor Networks

In this paper analytical models of the energy consumption are presented which uses a real world radio model with two different low power modes. This model is used to compare energy consumption of different MAC protocols. The MAC protocols used for the comparison are chosen with sensor networks is mind. The energy consumption of the nodes in a sensor network needs to be minimized to maximize the lifetime of the network. Emphasis is placed on MAC protocols, since they have a big influence on the energy consumption. One of the MAC protocols uses a low power Wake Up Receiver (WURx) which is used to decrease the total energy dissipation. The WURx MAC protocol is compared with two other low power MAC protocols, namely the asynchronous X-MAC and synchronous TDMA protocol. The obtained model is used to derive the WURx power budget. The response time of the nodes is used as the main design requirement and the important application parameters are given that determine the WURx power budget.

A novel Doherty amplifier for enhanced load modulation and higher bandwidth

We are reporting a new topology for the Doherty amplifier to increase its bandwidth and enhance the load modulation. A varactor-based impedance transformer has been employed to replace the bulky and narrowband quarter-wave impedance inverter. Load modulation is carried out adaptively using the proposed varactor-based structure based on the input power level. An envelope detector is employed for adaptive impedance transformation of the carrier amplifier as well as bias adaptation of the peak amplifier. Based on the proposed topology, a 2W Doherty amplifier has been fabricated using discrete pHEMT transistors and low loss varactors. In order to evaluate the broad-band/multi-band performance of the proposed topology, measurements have been carried out at three sample frequencies (1.8GHZ, 2GHz and 2.2GHz) over a 400 MHz bandwidth. Power added efficiency of better than 45.3% has been achieved at maximum power level and 6-dB power back-off and maintained over the entire bandwidth. Measured IM3 is better than −42.2dBc at P1dB of 33dBm for all design frequencies.

A 6b 10MS/s current-steering DAC manufactured with amorphous Gallium-Indium-Zinc-Oxide TFTs achieving SFDR > 30dB up to 300kHz

Amorphous Gallium-lndium-Zinc-Oxide (GIZO or IGZO) has been recently pro- posed [1] as an interesting semiconductor for manufacturing TFTs because of its mobility (μ~20cm7Vs), superior to other common materials for large-area elec- tronics like organic semiconductors and a-Si (μ~1cm7Vs). The amorphous nature of GIZO grants also a good uniformity, contrary to Low Temperature Polycrystalline Silicon (LTPS), which still offers the best mobility among large- area TFT technologies (μ~100cm2Λ/s). The optical transparency and the relative- ly low fabrication temperature (<;150°C) make this technology especially suitable for display backplanes and relative driving electronics [2], as well as for any kind of large-area applications on plastic foils, e.g. biomedical sensors, non-volatile memories [3], RFIDs [4], etc.

A 60GHz digitally controlled RF-beamforming receiver front-end in 65nm CMOS

Phased arrays form a crucial step towards high data rate 60GHz wireless communication. This paper presents a fully integrated digitally controlled 60GHz RF-beamforming receiver front-end in CMOS. Using digitally controlled active phase shifters, each path of the scalable architecture achieves 10dB power gain, 7.2dB noise figure, a 360° phase shift range in 22.5° steps at 61GHz, and a 3dB-bandwidth of 5.4GHz, while only dissipating 78mW in each path. Chip area is 1.6mm2.

Smart and flexible digital-to-analog converters

List Of Abbreviations. PART I: INTRODUCTION AND BASICS. 1. INTRODUCTION. 1.1. Modern Micro-Electronics And Flexibility. 1.2. Aims of the Book. 1.3. Scope of the Book. 1.4. Scientific Approach. 1.5. Outline of the Book. 2. BASICS OF DIGITAL-TO-ANALOG CONVERSION. 2.1. Introduction. 2.2. Functionality and Specifications. 2.3. DAC Resources. 2.4. Segmentation of DAC Analog Resources. 2.5. DAC Implementations. 2.6. Current-Steering DAC Architecture. 2.7. Modern Current-Steering DAC Challenges. 2.8. Summary. PART II: STATE-OF-THE-ART CORRECTION METHODS. 3. ERROR CORRECTION BY DESIGN. 3.1. Introduction. 3.2. Return-To-Zero Output. 3.3. Differential-Quad Switching. 3.4. Cascode Switches With Offset Current. 3.5. Input Data Reshuffling Methods (Dem). 3.6. Discussion. 3.7. Conclusions. 4. SMART SELF-CORRECTING D/A CONVERTERS. 4.1. Introduction. 4.2. Self-Calibration of DAC Current Cells. 4.3. Mapping. 4.4. Digital Pre-Distortion. 4.5. Discussion. 4.6. Conclusions. PART III: NEW MODELING, ANALYSIS, AND CLASSIFICATION. 5. ERROR MODELING FOR DAC CORRECTION, A BROAD VIEW. 5.1. Introduction. 5.2. A Model of the Step Response of a Current Cell. 5.3. Transistor Mismatch Caused Errors. 5.4. Digital-Switching Errors. 5.5. Discussion. 5.6. Conclusions. 6. BROWNIAN BRIDGE BASED ANALYSIS AND MODELING OF DAC LINEARITY, AN IN-DEPTH VIEW. 6.1. Introduction. 6.2. New Statistical Analysis of the DAC Static Non-Linearity Based on Brownian Bridge. 6.3. Discussion. 6.4. Conclusions. 7. CLASSIFICATION OF ERROR CORRECTION METHODS, A BROAD VIEW. 7.1. Introduction. 7.2. Selected Set of DAC Correction Methods And Definitions. 7.3. Error Measurement Category. 7.4. Redundancy Category. 7.5. System Level Category. 7.6. Discussion. 7.7. Conclusion. 8. ANALYSIS OF SELF-CALIBRATION OF CURRENTS, AN IN-DEPTH VIEW. 8.1. Introduction. 8.2. DAC Currents Self-Calibration Classification. 8.3. Self-Measurement. 8.4. Algorithm. 8.5. Self-Correction. 8.6. Conclusions. PART IV: NEW CONCEPTS AND METHODS. 9. NEW REDUNDANT SEGMENTATION CONCEPT. 9.1. Introduction. 9.2. Abstraction Levels Of Segmentation. 9.3. New Redundant Segmentation. 9.4. Discussion. 9.5. Conclusion. 10. NEW METHODS FOR SELF-CALIBRATION OF CURRENTS. 10.1. Introduction. 10.2. Self-Calibration Of Unary Currents. 10.3. A Calibration Method For Generic Current-Steering D/A Converters With Optimal Area Solution. 10.4. A Calibration Method For Binary Signal Current Sources. 10.5. Discussion. 10.6. Conclusions. 11. NEW REDUNDANT DECODER CONCEPT. 11.1. Introduction. 11.2. Conventional ROW-Column Decoder. 11.3. New Decoder With Redundancy. 11.4. Simulation Results. 11.5. Discussion. 11.6. Conclusions. 12. NEW HIGH-LEVEL MAPPING CONCEPT. 12.1. Introduction. 12.2. Conceptual Idea. 12.3. Illustrative Measurement And Simulation Results For Amplitude Errors Mapping. 12.4. Limitations And Discussion. 12.5. Conclusions. 13. NEW HARMONIC-DISTORTION-SUPPRESSION METHOD. 13.1. Introduction. 13.2. Theoretical Background. 13.3. Application Area. 13.4. Limitations and Discussion. 13.5. Conclusions. 14. FLEXIBLE DIGITAL-TO-ANALOG CONVERTERS CONCEPT. 14.1. Introduction. 14.2. Flexible DAC Platform. 14.3. Definitions Of Flexibility. 14.4. Operation Modes. 14.5. The Missing Code Problem. 14.6. Conclusions. PART V: DESIGN EXAMPLES. 15. A REDUNDANT BINARY-TO-THERMOMETER DECODER DESIGN. 15.1. Introduction. 15.2. Design Example. 15.3. Measurement Results And Discussion. 15.4. Conclusions. 16. TWO SELF-CALIBRATING DAC DESIGNS. 16.1. Introduction. 16.2. Unary Currents Self-Calibration In A 250nm DAC. 16.3. Both Unary And Binary Currents Self-Calibration In A 180nm DAC. 16.4. Comparison With State-Of-The-Art DAC Publications. 16.5. Conclusions. 17. A FUNCTIONAL-SEGMENTATION DAC DESIGN USING HARMONIC DISTORTION SUPPRESSION METHOD. 17.1. Introduction. 17.2. Test Set-Up Design. 17.3. Parallel Virtual Dacs. 17.4. Parallel Real Sub-DACs. 17.5. OFDM (Multi-Tone) System Application. 17.6. Conclusions. 18. A 14 BIT QUAD CORE FLEXIBLE 180NM DAC PLATFORM. 18.1. Introduction. 18.2. Design. 18.3. Measurements. 18.4. Conclusions. 19. A 16 BIT 16-CORE FLEXIBLE 40NM DAC PLATFORM. 19.1. Introduction. 19.2. Flexible DAC Platform Based On 16 Core Units. 19.3. Measurements. 19.4. Conclusions. PART VI: CONCLUSIONS. Summary. Conclusions. Appendix A. Published CMOS Digital-To-Analog Converters From 1986 Until 2009. References.

A 71GHz RF energy harvesting tag with 8% efficiency for wireless temperature sensors in 65nm CMOS

This paper presents the first monolithically integrated RF-power harvesting 71 GHz wireless temperature sensor node in 65nm CMOS technology, containing a monopole antenna, a 71 GHz RF power harvesting unit with storage capacitor array, an End-of-Burst monitor, a temperature sensor and an ultra-low-power transmitter at 79 GHz. At 71 GHz, the RF to DC converter achieves a power conversion efficiency of 8% for 5 dBm input power.

Wireless wire-the 60 GHz ultra-low power radio system

This article presents basic issues regarding design and development of a 60 GHz ultra-low power radio system for Ambient Intelligence (AmI) applications. It demonstrates the validity of choosing the 60 GHz frequency band to design low power radios by a mathematical model, and proposes an overview of a cross-layer optimization flow to minimize power dissipation. Moreover, a completed RF front-end architecture, i.e. the transmitter and the receiver, is simulated according to the proposed methodology. Crucial concerns, challenges and solutions are discussed based on it. Simulation results are given, which verify the theoretical conclusions of 120 pJ/bit power consumption.

Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption

This paper describes a method for analysis and design of MOS voltage-to-current converters (V-I converters or transconductors) and introduces a novel V-I converter circuit with significantly improved linearity performance. The proposed method uses harmonic compensation for the linearization of the V-I characteristics and introduces a normalized representation of the converter equations. The analysis is applied for several circuit topologies based on MOS differential pairs. The circuits are compared with respect to their current consumption, signal to noise ratio, achievable linearity and bandwidth. The minimum required current consumption for certain linearity and dynamic range is derived. The proposed novel V-I converter circuit uses a combination of local resistive feedback and cross-coupling. In this way, it achieves significant, simultaneous suppression of the third and the fifth order harmonic components in the transconductor output current. The implementation constraints and the performance of the new circuit solution are evaluated via simulations on transistor level. A standard digital 0.18 micrometer, 1.8V, CMOS process is used.

System analysis and energy model for radio-triggered battery-less monolithic wireless sensor receiver

Monolithic wireless sensors with integrated antenna, on-chip transceiving, sensing and energy scavenging are low-cost and robust, thus very suitable for mass production and deployment. The design of such a sensor node requires a proper architecture with careful trade-offs and joint considerations over different building blocks. In this paper, we focus on the energy scavenging and receiver part of such a sensor node. A radio-triggered receiver architecture is proposed to achieve the extreme low energy budget. Energy/power models for different building blocks are developed that show the tradeoffs between available energy and sensor performance. A system-level analysis identifies the 60GHz mm-wave band is suitable for such applications. Moreover, a design example of receiver front-end in 65nm CMOS technology is presented to demonstrate the potential performance of the proposed architecture.

A 155 /spl mu/W 88-dB DR Discrete-Time /spl Delta/ /spl Sigma/ Modulator for Digital Hearing Aids Exploiting a Summing SAR ADC Quantizer

This paper presents a low-power switched-capacitor ΔΣ modulator for digital hearing-aid applications that features a novel summing successive approximation (SAR). The summing SAR performs multi-bit quantization together with the analog addition required in feed-forward (FF) ΔΣ modulator (ΔΣM) topologies, with no attenuation of the input signals and no need for amplifiers. The prototype is implemented in a 0.18- μm CMOS technology and its measurements demonstrate a dynamic range of 88 dB in 10 kHz bandwidth while consuming 155 μW from a 1.8 V supply. The combined use of passive addition and SAR quantization reduces the complexity and power consumption of the modulator. The summing SAR ADC quantizer results in a calculated power saving of 40% when compared to a multi-bit FF ΔΣM using active addition and flash quantization.