Arun Joseph

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

We introduce a generalized, efficient, and accurate power abstraction model and generation techniques for complex IP blocks. This is based on the contributor based power modeling concept, which exploits the nature of power consuming components in a design being inherently separable. The generated power abstraction is Process, Voltage and Temperature (PVT) independent, thus enabling very efficient hierarchical power analysis. Our approach constitutes the industrys first design methodology to automatically generate PVT independent contributor based abstracts. We also describe extensions to the power contributor concept to model dynamic power. Extensive analysis and results on real industry designs to study the accuracy impacts of abstraction as a function of design types and sizes are presented. We also present model to hardware correlation experiments demonstrating the application of this abstraction based methodology on the IBM Power7+ server microprocessor chip.

FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware

Separating the dynamic power and leakage power components from total microprocessor power can enable new optimizations for cloud computing. To this end, we introduce FirmLeak, a new framework that enables accurate, real-time estimation of microprocessor leakage power by system software. FirmLeak accounts for power-gating regions, per-core voltage domains, and manufacturing variation. We present an experimental evaluation of FirmLeak on a POWER7+ microprocessor for a range of hardware parts, voltages and temperatures. We discuss how this can be used in two applications to manage power by 1) improving billing of energy for cloud computing and 2) optimizing fan power consumption.

Empirically derived abstractions in uncore power modeling for a server-class processor chip

Early-stage power modeling is an essential aspect of the process of defining efficient, yet high-performance microarchitectures. Pre-silicon power modeling has been an active area of research and development for well over a decade, although primarily focused on the processor cores. In this paper, we examine the challenge of developing practical abstractions in uncore power modeling in an industrial setting. We report a systematic methodology of abstractions in modeling with a focus on key uncore elements of the POWER8™ processor chip from IBM. The results show that the active power of these uncore elements can be modeled with acceptable levels of precision, by: (a) using just a few activity markers: e.g. reads, writes, retries and snoops; and (b) using a small set of systematically crafted microbenchmark stress test cases to measure the activity frequencies on a detailed, cycle- and latch-accurate RTL reference model.

Process Synchronization in Multi-core Systems Using On-Chip Memories

In this paper, we present a novel process synchronization mechanism and the application of on-chip memories for process synchronization in multi-core systems. The multi-core processor architecture and a signaling scheme which supports the novel process synchronization mechanism are presented. The validity of the proposed synchronization mechanism is demonstrated by experiments on a virtual prototyping platform. Also, comparison against external memory based schemes shows that the proposed use of on-chip memories in multi-core process synchronization is an effective solution to reduce synchronization overheads, especially as the number of processor cores increase.

FVCAG: A framework for formal verification driven power modeling and verification

Generation of accurate IP power models requires determination of correct simulation conditions for the different input pins of the IP. Determining such a set of inputs for individual IP blocks in a design is expensive in cost and time, and is also highly error prone. Additionally, it is desirable to identify IP instances in a design, where these simulation conditions are not met. These are relevant problems in the context of modern day microprocessor designs, which are designed using a very large number of IPs, either developed in-house or sourced from external vendors. In this paper, we examine these problems in an industrial context and introduce FVCAG, a framework for enabling efficient and accurate power modelling. FVCAG enables a more thorough IP power modelling than that can be accomplished using current state of the art techniques. Experimental evaluation of the proposed framework on the standard cell library and macros used in the design of an industry class high performance microprocessor design demonstrates the accuracy and efficiency of proposed framework.

Virtual logic netlist: Enabling efficient RTL analysis

Early design analysis is essential for better design definition and efficient balancing of design effort and risk. In this paper, we introduce the concept of virtual logic netlist (VLN), a potentially incomplete yet representative hierarchical and logical netlist graph of the design. VLN enables early and rapid register transfer level (RTL) analysis using accurate backend tool engines without the need for time-intensive synthesis techniques. We discuss the creation of a VLN, and its application to enable RTL clock gating analysis. Experimental evaluation performed on the IBM POWER8 microprocessor chip showed an error of less than 2%, and a TAT improvement of atleast 250x, when compared to full netlist based analysis.

FreqLeak: A frequency step based method for efficient leakage power characterization in a system

Accurate estimation of leakage power at runtime requires post-silicon power measurements across a wide range of temperature and voltage conditions. Testing individual chips, especially at high-temperature corner conditions, is expensive in cost and time. We examine this problem in an industrial context and introduce FreqLeak, a frequency step based method for inexpensive and efficient leakage power characterization in a system. It enables a more thorough characterization than can be accomplished on a wafer prober alone due to time and equipment costs. Experimental evaluation on IBM POWER8 based systems demonstrates the efficiency of the proposed method, within an error of 5%. Further, we discuss the application of FreqLeak in system level power management.