Anand Haridass

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

Optimum design of power distribution system via clock modulation

This paper presents a method for extracting current excitations, which a microprocessor (/spl mu/P) can present to its power distribution system (PDS) as a function of frequency. The method uses a clock modulation technique to measure the impedance seen by the uP.

Signal propagation over perforated reference planes

Voids on reference planes are commonly seen in organic chip packages and printed circuit boards. In this paper, the effects of these voids on the signal integrity of a high-density data bus will be studied. A generic FCPBGA chip package is used to illustrate the signal integrity concerns and perform sensitivity analysis on the key mechanisms including void size, adjacent plane interactions, and adjacent signal line interactions. The results show that proper design can mitigate the signal integrity impact of reference plane voids.

A case study of high-speed serial interface simulation with IBIS-AMI models

High-end, high-performance computers use high-speed serial interfaces to pass data and control signals between the electronic components in the systems. These interfaces include proprietary interfaces unique to a class of systems and some interfaces, such as PCIe & SAS, which have publicly available standards and specifications that enable communication between electronic components from different manufactures. The IBIS-AMI model has been developed to facilitate circuit simulation of high-speed serial interfaces and is particularly useful in simulating communication between transmitters and receivers procured from different manufactures. The simulations are performed to ensure that the interface specifications are met, including the eye characteristics, and that the bit error rate (BER) is less than a specified maximum. There are many variables and long bit strings needed to predict a BER of sufficiently low amplitude. Therefore, an efficient and accurate estimation of BER requires significantly long simulations times. In this paper, we use the example of a 6 gigabit per second (Gb/s) SAS interface to illustrate our proposed simulation method of combining an empirical and analytical approach to estimate the effects of inter-symbol interference (ISI) and channel jitter using an IBIS-AMI models.

Massively parallel full-wave modeling of advanced packaging structures on BlueGene supercomputer

A parallel, distributed memory version of a full wave method of moments (MoM) solution combined with the reduced coupling approximation technique is presented on the largest parallel-server. Modeling results for product-level simulation of a single-chip module are correlated with time- domain measurements for validation of the technique. Scaling for this and other representative examples are shown for up to 16,384 compute nodes on IBMs BlueGene supercomputer, the largest parallel-platform ever reported for MoM based solutions.

Efficient modeling methodology and hardware validation of glass-ceramic based wiring for high-performance single- and multi-chip modules

Ceramic-based wiring has been used in IBM in high-performance multi-chip module (MCM) carriers since the early 1980s. These types of carriers can provide very high wiring and power densities. Conductors are generally screened on individual ceramic sheets that are laminated and sintered at greater than 900/spl deg/ C. The high temperature process requires the use of copper paste metallization with higher resistivity than bulk copper and the punched-via fabrication imposes the use of meshed ground planes. Typical MCMs can have close to 100 layers [George Katopis (1998)] with 200-400 /spl mu/m via pitch. In the case of single-chip modules (SCM), hundreds of signal I/Os on 100-200 /spl mu/rn pitch redistribute to the coarser module wiring. The fan-out, the hollow shielding, and the sparse and long vias generate large signal distortion and crosstalk between signal layers and via columns. This paper describes the modeling and measurement of representative glass-ceramic based wiring for both SCM and MCM applications.

Methodology for minimizing far-end noise coupling between interconnects in high-speed ceramic modules

In this paper, we present a methodology for minimizing far-end (FE) noise coupling between interconnects in high-speed ceramic modules. The high FE noise coupling between signal interconnects in ceramic modules has been a serious bottleneck for high-performance systems. A methodology employing power/ground mesh planes with minimized orthogonal lines and a via-connected coplanar-type shield (VCS) structure has been developed to minimize FE noise coupling between signal lines in ceramic modules. Optimized interconnect structure based on this methodology has demonstrated that the saturated FE crosstalk of a typical interconnect structure in ceramic modules could be reduced significantly by 88.7 %.

FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware

Separating the dynamic power and leakage power components from total microprocessor power can enable new optimizations for cloud computing. To this end, we introduce FirmLeak, a new framework that enables accurate, real-time estimation of microprocessor leakage power by system software. FirmLeak accounts for power-gating regions, per-core voltage domains, and manufacturing variation. We present an experimental evaluation of FirmLeak on a POWER7+ microprocessor for a range of hardware parts, voltages and temperatures. We discuss how this can be used in two applications to manage power by 1) improving billing of energy for cloud computing and 2) optimizing fan power consumption.

Crosstalk Analysis between Interconnects in High-Speed Server Packages

This paper discusses crosstalk analysis between interconnects in high-speed server packages. Over the last decade, the scaling of the CMOS transistors has enabled the design of microprocessors operating at multi-gigahertz frequencies. For meeting the high bandwidth demands and low-power requirements, digital technologies are quickly moving to gigabit data rate and sub-voltage range signaling levels. However, this higher speed performance comes at a price, which means that signal integrity becomes a significant portion of the design effort. Especially, crosstalk analysis between interconnects in high-speed packages has become critical for design optimization of signal interconnects in system. This paper investigates importance of crosstalk analysis for IBMs high-speed server packages. For an efficient crosstalk analysis between interconnects in highspeed digital systems, an IBMs internal tool called PATS (package analysis tool suite) was used to investigate crosstalk over 1000 signal nets. The ISNRR (integral of squared noise ramp response) method has been developed to quantify crosstalk accurately and used to analyze IBMs organic modules for high-speed applications.

IBM Power5 bus designs for on- and off-module connections

This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.