Arunkumar Vijayakumar

A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics

Physical Unclonable Function (PUF) circuits are used for chip authentication. PUF designs rely on manufacturing process variations to produce unique response to input challenges. It has been shown that many PUF designs are vulnerable to machine learning (ML) attacks, where a model can be built to predict PUF response to any input after only a few observations. In this work, we propose a ML attack resistant PUF design based on a circuit block to implement a non-linear voltage transfer function. The proposed circuit is simple, exhibits high uniqueness and randomness. Further improvements are proposed to enhance PUF reliability. The proposed circuit was simulated in a 45nm technology process and the results indicate a significant improvement in ML attack resistance in comparison to traditional PUFs. Results on uniqueness and reliability are also presented.

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this paper, we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. The examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist, which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature. In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

Machine learning resistant strong PUF: Possible or a pipe dream?

Physically unclonable functions (PUFs) are emerging as hardware primitives for key-generation and light-weight authentication. Strong PUFs represent a variant of PUFs which respond to a user challenge with a response determined by its unique manufacturing process variations. Unfortunately many of the Strong PUFs have been shown to be vulnerable to model building attacks when an attacker has access to challenge and response pairs. In mounting a model building attack, typically machine learning is used to build a software model to forge the PUF. Researchers have long been interested in designing Strong PUFs that are resistant to model building attacks. However, with innovations in application of machine learning, nearly all Strong PUFs presented in the literature have been broken. In this paper, first we present results from a set of experiments designed to show that if certain randomness properties can be met, cascaded structure based Strong PUFs can indeed be made machine learning (ML) attack resistant against known ML attacks. Next we conduct machine learning experiments on an abstract PUF model using Support Vector Machines, Logistic Regression, Bagging, Boosting and Evolutionary techniques to establish criteria for machine learning resistant Strong PUF design. This paper does not suggest how to harvest the process variation, which remains within the purview of a circuit designer; rather it suggests what properties of the building blocks to aim for towards building a machine learning resistant Strong PUF - thus paving the path for a systematic design approach.

A Chaotic Ring oscillator based Random Number Generator

True Random Number Generator (TRNG) circuits play an important role in hardware security. Traditional Ring Oscillator (RO) based TRNGs aim to amplify thermal noise and supply noise jitters. To increase randomness, traditional RO based TRNGs harvest random noise from large number of stages resulting in large area and power. We propose a Chaotic Ring oscillator based random number Generator (CRNG) for CMOS implementation. This circuit uses nonlinear elements which are straightforward to implement in CMOS to bring about chaotic behavior. We demonstrate that the proposed CRNG passes tests for randomness and are immune to modeling attacks. Albeit small in magnitude, the proposed CRNG also harvests physical noise which acts as a compounder over chaos. The proposed CRNG circuit is small in area, scales well with technology, operates at low voltages and does not require any special manufacturing process. The output bit stream of the proposed CRNG implemented in a 45 nm process was tested using the NIST test suite and it passes 11 tests. Results show that the proposed CRNG occupies an area of 93.1 μm2 and has a throughput of 127 Mbps at a power of 1.1 mW. This compares very well against state of the art TRNGs.

On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors

Recent trends in CMOS technology scaling have resulted in increased transistor density, higher clock speed and reduced cost per transistor. However technology scaling has also resulted in increased Power Supply Noise (PSN). Power supply noise can result in erroneous computation, reduced performance and lower reliability. Current PSN detectors require either golden supply voltage as reference or bulky analog to digital conversion circuits. This paper introduces a novel PSN detector for active power management in Microprocessors. The proposed detector makes use of the dynamic shift in Voltage Transfer Characteristics(VTC) of an inverter due to supply noise. Simulation results of the proposed PSN detector in 45-nm CMOS technology shows that the detector can detect overshoots or undershoots as small as 10 mV and 100 ps wide. Moreover, the detector works with 10 mV accuracy for a wide temperature range.

On testing physically unclonable functions for uniqueness

A number of applications from smartcard to ePassport to eID depend on preventing unauthorized access to hardware and software functionality. Physically Unclonable Functions (PUF) rely on manufacturing process variations to create unique identifiers that can be used for various security applications including authentication and secure access. For practical applications, PUFs are required to be unique for each chip. Such property cannot be ensured by design alone. Since PUFs rely on manufacturing process variations, there are no guarantees that two PUFs will never have identical properties. Therefore, testing becomes necessary to screen out PUFs that violate the above property. Despite decades of research on PUFs, there has been scant attention to the problem of testing PUFs for uniqueness. In this paper, we investigate the problem of testing PUFs for uniqueness and we propose techniques for Uniqueness testing. The proposed methods are low-cost and are tailored for testing PUFs using hardware testers.

An Efficient Method for Clock Skew Scheduling to Reduce Peak Current

Concurrent switching of flip-flops and logic gates produces a current surge in synchronous circuits resulting in power supply noise and integrity issues. It is well known that peak current caused by simultaneous switching can be reduced by clock skew scheduling. It has been shown that this problem may be formulated as an integer linear programming problem. However, such formulation is computationally expensive for designs with large number of flip-flops. In this work, we propose a fast heuristic method to schedule clock skew for reducing peak current. The proposed method is evaluated on ISCAS-89, ITC99 and synthetic benchmark circuits. Results show that the proposed method finds a near-optimal solution within minutes even for the largest benchmark circuits.

On pattern generation for maximizing IR drop

Increase in power density and decrease in supply voltage results in greater power supply current. With scaling, line resistance increases. Together with increase in supply current, this results in ever larger IR drop in supply voltage. IR drop analysis is an important element of power supply network design. Maximizing IR drop is also an important component of manufacturing testing. As a CMOS gate primarily draws current during switching, IR drop maximization problem is akin to finding input pattern pair that maximizes circuit switching taking the drive strengths of the gates and their spatial distribution into consideration. In this paper, we examine IR-drop analysis problem for combinational circuits. The solution to the general problem of maximizing IR drop of a power supply network can be reformulated as a pattern generation problem to maximize IR drop at a specific point on the power supply network, as this analysis can then be applied on a collection of target points determined by load distribution on the grid. The main contributions of this paper are (i) formulation of objective function for pattern generation using the spatial location and strengths of the gates and (ii) expressing the Boolean relationships between gates to use in an Integer Linear Programming solver for solving the pattern generation problem. We further show that by exploiting the conic structure of combinational circuits and the proposed formulation of objective function, the technique is easily applied to larger circuits. The proposed technique was applied to ISCAS-85 benchmark circuits and validated in simulation. Results show that with targeted pattern generation and deterministic approach, we achieve ~25 % moreIR drop over random patterns on an average, while average run-time improves by four orders of magnitude.

Glitch Power Reduction via Clock Skew Scheduling

Dynamic power consumption is directly related tothe number of the signal transitions in a circuit. Glitches are undesired spurious transitions caused by inputs of a gate arriving at different times, instead of arriving together, thus causing unnecessary power dissipation. Our objective in this paper is to reduce the number of glitches in a circuit to reduce dynamic power. We do so by clock skew scheduling, where different flipflopsreceive clocks at different times. We formulate thescheduling as an Integer linear Programming problem andderive vector-independent clock skew schedule to reduce glitches. We also propose linear objective functions based on timing window of gates for optimization. The proposed method was evaluated on ISCAS-89 benchmark circuits using dynamic simulation. Results show that we achieve an average reduction of ~32% in glitch power.

A system-level solution for managing spatial temperature gradients in thinned 3D ICs

As conventional CMOS technology is approaching scaling limits, the shift in trend towards stacked 3D Integrated Circuits (3D IC) is gaining more importance. 3D ICs offer reduced power dissipation, higher integration density, heterogeneous stacking and reduced interconnect delays. In a 3D IC stack, all but the bottom tier are thinned down to enable through-silicon vias (TSV). However, the thinning of the substrate increases the lateral thermal resistance resulting in higher intra-layer temperature gradients potentially leading to performance degradation and even functional errors. In this work, we study the effect of thinning the substrate on temperature profile of various tiers in 3D ICs. Our simulation results show that the intra-layer temperature gradient can be as high as 57°C. Often, the conventional static solutions lead to highly inefficient design. To this end, we present a system-level situation-aware integrated scheme that performs opportunistic thread migration and dynamic voltage and frequency scaling (DVFS) to effectively manage thermal violations while increasing the system throughput relative to stand-alone schemes.