Vinay C. Patil

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this paper, we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. The examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist, which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature. In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

Machine learning resistant strong PUF: Possible or a pipe dream?

Physically unclonable functions (PUFs) are emerging as hardware primitives for key-generation and light-weight authentication. Strong PUFs represent a variant of PUFs which respond to a user challenge with a response determined by its unique manufacturing process variations. Unfortunately many of the Strong PUFs have been shown to be vulnerable to model building attacks when an attacker has access to challenge and response pairs. In mounting a model building attack, typically machine learning is used to build a software model to forge the PUF. Researchers have long been interested in designing Strong PUFs that are resistant to model building attacks. However, with innovations in application of machine learning, nearly all Strong PUFs presented in the literature have been broken. In this paper, first we present results from a set of experiments designed to show that if certain randomness properties can be met, cascaded structure based Strong PUFs can indeed be made machine learning (ML) attack resistant against known ML attacks. Next we conduct machine learning experiments on an abstract PUF model using Support Vector Machines, Logistic Regression, Bagging, Boosting and Evolutionary techniques to establish criteria for machine learning resistant Strong PUF design. This paper does not suggest how to harvest the process variation, which remains within the purview of a circuit designer; rather it suggests what properties of the building blocks to aim for towards building a machine learning resistant Strong PUF - thus paving the path for a systematic design approach.

Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain

Physically Unclonable Functions (PUFs) are a class of circuits, which are used to map a set of challenges to responses relying upon the intrinsic process variations in interconnects and transistors. The PUFs are expected to produce unique and repeatable responses. In an arbiter based PUF, the uniqueness is contingent upon relative path delays. Reliability or repeatability of responses depends on circuit sensitivity to environmental parameters such as temperature. In this paper, we propose an arbiter based PUF circuit built on current starved inverters, whose drain currents are set by local current mirrors. This circuit amplifies process variations that result in greater uniqueness when compared against a simple inverter chain. The final 64-stage PUF implemented in 45nm CMOS technology requires only 256 current-starved inverter gates. In experimental results we demonstrate superior performance of proposed circuit in uniqueness and reliability.

On testing physically unclonable functions for uniqueness

A number of applications from smartcard to ePassport to eID depend on preventing unauthorized access to hardware and software functionality. Physically Unclonable Functions (PUF) rely on manufacturing process variations to create unique identifiers that can be used for various security applications including authentication and secure access. For practical applications, PUFs are required to be unique for each chip. Such property cannot be ensured by design alone. Since PUFs rely on manufacturing process variations, there are no guarantees that two PUFs will never have identical properties. Therefore, testing becomes necessary to screen out PUFs that violate the above property. Despite decades of research on PUFs, there has been scant attention to the problem of testing PUFs for uniqueness. In this paper, we investigate the problem of testing PUFs for uniqueness and we propose techniques for Uniqueness testing. The proposed methods are low-cost and are tailored for testing PUFs using hardware testers.

An Efficient Method for Clock Skew Scheduling to Reduce Peak Current

Concurrent switching of flip-flops and logic gates produces a current surge in synchronous circuits resulting in power supply noise and integrity issues. It is well known that peak current caused by simultaneous switching can be reduced by clock skew scheduling. It has been shown that this problem may be formulated as an integer linear programming problem. However, such formulation is computationally expensive for designs with large number of flip-flops. In this work, we propose a fast heuristic method to schedule clock skew for reducing peak current. The proposed method is evaluated on ISCAS-89, ITC99 and synthetic benchmark circuits. Results show that the proposed method finds a near-optimal solution within minutes even for the largest benchmark circuits.

On pattern generation for maximizing IR drop

Increase in power density and decrease in supply voltage results in greater power supply current. With scaling, line resistance increases. Together with increase in supply current, this results in ever larger IR drop in supply voltage. IR drop analysis is an important element of power supply network design. Maximizing IR drop is also an important component of manufacturing testing. As a CMOS gate primarily draws current during switching, IR drop maximization problem is akin to finding input pattern pair that maximizes circuit switching taking the drive strengths of the gates and their spatial distribution into consideration. In this paper, we examine IR-drop analysis problem for combinational circuits. The solution to the general problem of maximizing IR drop of a power supply network can be reformulated as a pattern generation problem to maximize IR drop at a specific point on the power supply network, as this analysis can then be applied on a collection of target points determined by load distribution on the grid. The main contributions of this paper are (i) formulation of objective function for pattern generation using the spatial location and strengths of the gates and (ii) expressing the Boolean relationships between gates to use in an Integer Linear Programming solver for solving the pattern generation problem. We further show that by exploiting the conic structure of combinational circuits and the proposed formulation of objective function, the technique is easily applied to larger circuits. The proposed technique was applied to ISCAS-85 benchmark circuits and validated in simulation. Results show that with targeted pattern generation and deterministic approach, we achieve ~25 % moreIR drop over random patterns on an average, while average run-time improves by four orders of magnitude.

Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment

The number of devices that are being connected by the Internet is growing rapidly and hence, safeguarding private information by incorporating hardware and software security measures has become crucial. Physically unclonable functions (PUFs) have been proposed to enable lightweight hardware security which uses the inherent manufacturing variations as a way to generate unique signatures. However, given largescale applications like the Internet of Things (IoT) that need to distinguish between millions of devices, it is an arduous task to identify a particular device that generates its signature using a PUF. Unreliable signatures due to various sources of noise complicate the problem that may lead to misidentification. This paper explores the various constraints for use of PUFs for largescale authentication and develops certain minimum requirements on PUF utilization that can aid system designers in making informed decisions.

Manufacturer turned attacker: Dangers of stealthy trojans via threshold voltage manipulation

Applications of Integrated Circuits (ICs) have become pervasive. A striking feature of the contemporary IC industry is that a very large and growing proportion of the IC foundries are now located offshore. While offshoring IC production reduces cost, it also creates a concern that the functionality of the circuits may be compromised by Trojans designed to cause malfunction at a select times. This concern is particularly acute in defense, energy and infrastructure systems. Extensive research has been conducted into detection of Trojans which involve either modification of existing circuitry or addition of extra logic. Some Trojans do not involve addition of logic or modification of physical design - they manipulate existing structures to behave differently. Such Trojans, known as stealthy Trojans, are particularly hard to detect. This work explores utilization of multi-threshold logic and threshold voltage manipulation as an attack vector to introduce stealthy Trojans. Also, a previously unexplored method of using the temperature of the device to, selectively, activate a Trojan is studied. Our work illustrates an attack on a D flip-flop, where we show that the threshold voltages can be manipulated to introduce a permanent stuck-at fault. Further, we show that the manipulation can allow the flipflop to work normally at 25°C while becoming dysfunctional at 60°C. In this paper, we discuss how this feature can be used to compromise the security of cryptographic functions.

Determining proximal geolocation of IoT edge devices via covert channel

Many IoT devices are part of fixed critical infrastructure, where the mere act of moving an IoT device may constitute an attack. Moving pressure, chemical and radiation sensors in a factory can have devastating consequences. Relocating roadside speed sensors, or smart meters without knowledge of command and control center can similarly wreck havoc. Consequently, authenticating geolocation of IoT devices is an important problem. Unfortunately, an IoT device itself may be compromised by an adversary. Hence, location information from the IoT device cannot be trusted. Thus, we have to rely on infrastructure to obtain a proximal location. Infrastructure routers may similarly be compromised. Therefore, there must be a way to authenticate trusted routers remotely. Unfortunately, IP packets may be blocked, hijacked or forged by an adversary. Therefore IP packets are not trustworthy either. Thus, we resort to covert channels for authenticating Internet packet routers as an intermediate step towards proximal geolocation of IoT devices. Several techniques have been proposed in the literature to obtain the geolocation of an edge device, but it has been shown that a knowledgeable adversary can circumvent these techniques. In this paper, we survey the state-of-the-art geolocation techniques and corresponding adversarial countermeasures to evade geolocation to justify the use of covert channels on networks. We propose a technique for determining proximal geolocation using covert channel. Challenges and directions for future work are also explored.

A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF

SRAM-based Weak PUFs have become popular in tamper sensitive key storage and device ID generation. Weak PUFs rely on intrinsic process variations to produce repeatable and unique start-up behavior. However, noise in the system compromises repeatability of SRAM start-up behavior. To obviate this problem, a number of solutions such as fuzzy extraction and error correcting codes have been proposed to generate a stable key from error-prone PUF cells. Unfortunately, the overhead from these techniques grows superlinearly with increasing error rate. Recently, it was suggested that the start-up error rate can be reduced significantly by accelerating device aging, which leads to reduced overhead for error correction. To accelerate aging, devices are subjected to temperature and voltage stress in a burn-in chamber. Unfortunately, burn-in accrues significant production cost. In this paper, we present a method to reduce the cumulative burn-in time by quantifying the minimum burn-in requirement for each device. We propose a low-cost proxy to measure the degree of process variation of each device at birth and use previously proposed device aging model to determine the burn-in requirements. Our results show that this procedure reduces cumulative burn-in cost without compromising the resultant reliability of Weak PUFs.