Raghavan Kumar

On design of a highly secure PUF based on non-linear current mirrors

Physically Unclonable Functions (PUFs) are lightweight hardware security primitives for generating unique signatures from the unpredictable nature of silicon. However, most of the proposed PUFs have been shown to be vulnerable to modeling attacks, especially against Machine Learning algorithms. A subset of challenge-response pairs can leak the required information to break a PUF due to the presence of a linear separating boundary between the PUF responses. In this paper, we propose a strong and secure PUF based on non-linear current mirrors. The fundamental idea is to propagate a current through two identical chains of non-linear current mirrors. The current through a single stage is shifted by some amount based on the strength of the input current. As the current shift is not a fixed value anymore, strong non-linearity is introduced into the challenge-response relationship. The proposed PUF shows excellent properties upon statistical circuit simulation. The average inter-distance and intra-distance of the proposed PUF are 49.9% and 0.8% respectively. One of the most striking features of the proposed PUF is the low information leakage measured in terms of its modeling attack resistance. By employing Support Vector Machine (SVM) based attacks, we observed that the proposed PUF is almost 10-30x stronger than the delay-based PUFs. Moreover, the current mode nature of the PUF circuit enables low power operation. The proposed PUF consumes about 15% lower energy than an arbiter PUF to produce a single response bit.

Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware

We propose two extremely stealthy hardware Trojans that facilitate fault-injection attacks in cryptographic blocks. The Trojans are carefully inserted to modify the electrical characteristics of predetermined transistors in a circuit by altering parameters such as doping concentration and do pant area. These Trojans are activated with very low probability under the presence of a slightly reduced supply voltage (0.001 for 20% Vdd reduction). We demonstrate the effectiveness of the Trojans by utilizing them to inject faults into an ASIC implementation of the recently introduced lightweight cipher PRINCE. Full circuit-level simulation followed by differential cryptanalysis demonstrate that the secret key can be reconstructed after around 5 fault-injections.

On improving reliability of delay based Physically Unclonable Functions under temperature variations

Physically Unclonable Functions (PUFs) are a special class of circuits used for challenge-response authentication. The challenge-response pair for PUFs should be mathematically unpredictable, but must be reliable and remain unvarying. The reliability of PUFs implemented in CMOS circuits is frequently compromised by environmental conditions such as voltage and temperature. In this paper, we propose two methods for improving the reliability of delay based PUFs, by reducing temperature sensitivity. The first method focuses on improving the gate overdrive (VGS − Vt(T)), by operating the PUF at an optimized supply voltage (V′DD), also called as ZTC (Zero Temperature Coefficient) voltage. The optimum supply voltage for a 24 stage PUF is almost 23% lower than the nominal supply voltage in 45nm CMOS technology. The second method exploits the negative temperature coefficient (TCR) property of n+ and p+ polysilicon placed as source feedback resistors. A 16% improvement in reliability has been demonstrated for both the methods. Moreover, we also demonstrate that these design optimizations do not compromise the PUF uniqueness.

Protecting cryptographic hardware against malicious attacks by nonlinear robust codes

Fault-based attacks against cryptographic circuits must be addressed by techniques that are different from approaches designed for random transient faults. We systematically investigate robust error-detecting codes that specifically target malicious attacks and guarantee minimal bounds on detection probability. Our study is based on FPGA-supported fault-injection campaigns on the circuit implementation of a recent lightweight block cipher and its sub-modules. We quantify the detection capabilities of different robust and non-robust codes with respect to both random faults and malicious attacks, as well as the required overheads. For the first time, we report performance of a novel punctured cubic code on actual cryptographic circuitry. Experimental results show that robust codes with a certain number of redundant bits have better detection properties in security context and higher predictability than their conventional linear counterparts.

Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain

Physically Unclonable Functions (PUFs) are a class of circuits, which are used to map a set of challenges to responses relying upon the intrinsic process variations in interconnects and transistors. The PUFs are expected to produce unique and repeatable responses. In an arbiter based PUF, the uniqueness is contingent upon relative path delays. Reliability or repeatability of responses depends on circuit sensitivity to environmental parameters such as temperature. In this paper, we propose an arbiter based PUF circuit built on current starved inverters, whose drain currents are set by local current mirrors. This circuit amplifies process variations that result in greater uniqueness when compared against a simple inverter chain. The final 64-stage PUF implemented in 45nm CMOS technology requires only 256 current-starved inverter gates. In experimental results we demonstrate superior performance of proposed circuit in uniqueness and reliability.

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Physically Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from complex and irreproducible manufacturing variations. The uniqueness of a PUF is a fundamental performance metric that defines the extent to which a response is tied to a single device. It is often compromised if the manufacturing variations are suppressed. Though attempts have been made to improve the quality of a PUF at system level, very little work has been done at enhancing the impact of manufacturing variations on PUF circuits. In this work, we propose a novel generalized systematic framework for improving inter-die and inter-wafer manufacturing variations of a PUF circuit. The framework aligns the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. We validated the proposed technique using a large population sample of arbiter PUFs. Simulation results show that the proposed scheme has improved inter-die and inter-wafer uniqueness of arbiter PUFs by as much as 8.4% and 16% respectively. The framework can be applied to any delay-based silicon PUF structure.

Litho-aware and low power design of a secure current-based physically unclonable function

Physically Unclonable Functions (PUFs) are lightweight cryptographic primitives for generating unique signatures from complex manufacturing variations. In this work, we present a current-based PUF designed using a generalized lithographic simulation framework for improving inter-die and inter-wafer uniqueness. The sensitivity of the circuit to manufacturing variations is enhanced by placing the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. Simulation results show that the litho-aware current based PUF has improved inter- and intra-distance over the conventional current-based PUF. The litho-aware PUF consumes about 0.034 pico joules of energy per response bit, which is substantially better than delay-based PUF implementations.

A high-speed cryogenic SiGe channel combiner IC for large photon-starved SNSPD arrays

In this paper, the design and characterization of a cryogenic eight-channel pixel combiner circuit designed to readout superconducting nanowire single photon detectors (SNSPDs) is presented. The circuit is designed to amplify, digitize, edge detect, and combine the output signals of an array of eight SNSPDs. The design has been enabled by the development of novel large-signal cryogenic HBT simulation models. The circuit has been fabricated and measurement results demonstrate excellent agreement with simulation.

On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors

Recent trends in CMOS technology scaling have resulted in increased transistor density, higher clock speed and reduced cost per transistor. However technology scaling has also resulted in increased Power Supply Noise (PSN). Power supply noise can result in erroneous computation, reduced performance and lower reliability. Current PSN detectors require either golden supply voltage as reference or bulky analog to digital conversion circuits. This paper introduces a novel PSN detector for active power management in Microprocessors. The proposed detector makes use of the dynamic shift in Voltage Transfer Characteristics(VTC) of an inverter due to supply noise. Simulation results of the proposed PSN detector in 45-nm CMOS technology shows that the detector can detect overshoots or undershoots as small as 10 mV and 100 ps wide. Moreover, the detector works with 10 mV accuracy for a wide temperature range.

Hybrid modeling attacks on current-based PUFs

Physically Unclonable Functions have emerged as a possible candidate to replace traditional cryptography. However, majority of the strong PUFs are vulnerable to modeling attacks. In this work, we take a closer look at the possible attacks on one of the strong PUF architectures known as Current-based PUFs, which exploit irregularities in transistor currents to generate unique signatures. We demonstrate that the fault-injection attacks when coupled with a machine learning (ML) algorithm can considerably push the limits of prediction accuracies. Based on simulations, we observed that the stand-alone ML algorithms suffer from error prone CRPs especially for higher length PUFs. In such scenarios, hybrid attacks exploiting the unreliable responses pushed the prediction accuracies up to 99% for higher length Current-based PUF circuits.