Arup Polley
Texas Instruments
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Publication
Featured researches published by Arup Polley.
symposium on vlsi circuits | 2016
Ajit Sharma; Seung Bae Lee; Arup Polley; Sriram Narayanan; Wen Li; Terry L. Sculley; Srinath Ramaswamy
A multi-modal analog front end (AFE) and ultra-low energy bio-sensing CMOS SoC is presented. System/ circuit techniques enable signal path duty cycles as low as sub-1% and result in a 35μA Photo Plethysmography (PPG) RX Chain - 5X lower than published state of the art - while maintaining overall SNR > 80dBFS. The signal chain is adaptively synchronized by an ultra-low power FSM and includes a 1.3μW 14b 1kSPS SAR A/D. Input signal-aware, real-time data path adaptation is achieved by leveraging on-the-fly algorithms running on an external microcontroller (μC) to further reduce system energy. A programmable, asynchronous capacitive reset amplifier (PARCA) with NEF of 4.8 and dx/dt analog feature extractor demonstrate energy efficient ECG capture. A battery-powered, Bluetooth low energy (BLE) based, wearable platform with simultaneous ECG and PPG acquisition using this AFE has been demonstrated.
Archive | 2004
Arup Polley; Rajarshi Mukhopadhyay; Reza Sharifi; Mark Wolfe
Archive | 2014
Arup Polley
Archive | 2016
Ajit Sharma; Seimg Bae Lee; Srinath Ramaswamy; Sriram Narayanan; Arup Polley
Archive | 2016
Arup Polley; Archana Venugopal; Robert R. Doering; Luigi Colombo
IEEE Journal of Solid-state Circuits | 2017
Ajit Sharma; Arup Polley; Seung Bae Lee; Sriram Narayanan; Wen Li; Terry L. Sculley; Srinath Ramaswamy
Archive | 2015
Arup Polley; Archana Venugopal; Luigi Colombo; Robert R. Doering
Archive | 2016
Arup Polley; Russell M. Rosenquist; Terry L. Sculley
Archive | 2015
Ajit Sharma; Seung Bae Lee; Srinath Ramaswamy; Sriram Narayanan; Arup Polley
Archive | 2015
Ajit Sharma; Sriram Narayanan; Srinath Ramaswamy; Arup Polley; Seung Bae Lee; Wen Li