Terry L. Sculley

Combining subband decomposition and sigma delta modulation for wideband A/D conversion

This paper describes a method of digitizing a wide-band signal by performing subband decomposition via a bank of tuned bandpass sigma-delta modulators. Each modulator only converts a portion of the signal spectrum, increasing the effective oversampling ratio for the wide-band signal by the number of parallel modulators. A prototype bandpass /spl Sigma//spl Delta/ modulator with a programmable noise null was fabricated in a 2 /spl mu/m CMOS process and used to construct a four channel parallel A/D conversion system.<<ETX>>

A Fourth Order Bandpass Delta-Sigma Modulator with DigitallyProgrammable Passband Frequency

The design and implementation of a fourth order switched-capacitorbandpass delta-sigma modulator with digitally programmable passbandis described. The quantization noise null can be programmed from0.4π (0.2f_s) to 0.6π(0.3f_s) in steps of 0.01π (f_s/200)by changing digital switch settings. This design enables theA/D conversion of a bandpass signal with digital tuning of thecenter frequency for application in systems such as a transceiverIF stage. The modulator IC measures 4.8mm2 in a2µ m CMOS process and achieves an SNR of 47 and59 dB over a 0.01π bandwidth at sampling ratesof 2.358 MHz and 1.25 MHz, respectively.

Design and implementation of bandpass delta-sigma modulators using half-delay integrators

Two bandpass delta-sigma A/D converters using half delay, integrators have been designed and implemented in a 2-/spl mu/m n-well double-poly double-metal CMOS process. The first design, a fourth-order architecture with an input modulation network, achieves a signal-to-noise ratio (SNR) of 73 dB over a 0.005/spl pi/ input bandwidth, while the second design, a sixth-order topology, yielded a measured SNR of 80 dB over a 0.004/spl pi/ input bandwidth.

A 16-bit current sample/hold circuit using a digital CMOS process

In current-mode circuits clock feedthrough from sampling switches is a major source of error. While this error can be reduced to only an offset in switched-capacitor circuits, it produces more severe nonlinearities in switched-current designs. If the input is held constant over several cycles, clock feedthrough errors can be significantly reduced, but for a dynamic input, the ultimate solution has been to use a large sampling capacitor and small-switches. We propose a method of building a highly accurate oversampling current-mode sample/hold circuit using feedback architectures. First, second, and third-order feedback structures are proposed and simulated, with the results showing increased precision as oversampling ratio increases. A 16-bit current sample/hold circuit using a standard digital 2 /spl mu/m CMOS process is presently being designed and fabricated.<<ETX>>

Nonlinearity correction techniques for high speed, high resolution A/D conversion

In general, low resolution circuitry can be designed with higher speed performance than high resolution circuitry. Most high resolution A/D converter architectures require a high resolution component, such as a S/H or integrator, in their design and are often limited by the speed of this component. This paper discusses several techniques for achieving high resolution A/D conversion by calibrating nonlinear circuitry with highly accurate reference circuitry without conversion speed being limited by the calibration circuitry. The analysis of a sample converter with various nonidealities is presented, along with supporting simulation results for a similar architecture. >

Oversampling current sample/hold structures for digital CMOS process implementation

The inaccuracies obtained by sampling a dynamic input signal is a major source of error in current-mode circuits. A sampled-data feedback architecture is presented for the design of a high-linearity current sample/hold that uses oversampling to overcome the nonlinearity of internal components. Both system and circuit level considerations are discussed, culminating in the design and implementation of both first- and second-order structures in a 2 /spl mu/m p-well CMOS process. Limited test results show a linearity of up to 69 dB at a sampling rate of 5 MHz. These circuits provide an excellent sampling stage for the realization of a high-resolution current-mode /spl Delta//spl Sigma/ A/D converter in a digital CMOS process.

Discrete-time feedback structures for high precision analog signal processing

The use of purely discrete-time analog feedback circuits with no continuous-time feedback present is described for realizing high precision analog signal processing systems. Several attractive properties of these systems are discussed, and their application as a highly linear current-mode sample/hold is presented.

A multilayer neural network structure for analog filtering

The design of analog filters has been a topic of research for many years, yielding a wide variety of techniques for addressing the problem. The work described here approaches this task from a neural network perspective to obtain some of the advantages of neural systems, such as a high tolerance to component imprecision and an ability to train or adapt high-order structures. Investigations of linear filter networks utilizing neural-like system topologies are presented, along with accompanying training algorithms and simulation results. Design of a reduced interconnect network in 2 /spl mu/m CMOS is suggested, with simulations indicating its potential for implementing high order, self-programming analog filters at bandwidths above 70 MHz.

A neural network approach to high performance analog circuit design

In order to gain new insight into the design of high-precision, high-speed analog circuits, several possible network implementations of an A/D convertor are presented. These networks are marked by programmability and parallelism, which can be used to maintain circuit precision without the use of feedback. This removes design constraints on closed-loop stability, and may lead to faster circuit performance. On-chip training or calibration is likely to be necessary, but can be done in an offline mode, and thus may not hinder circuit speed significantly.<<ETX>>

An enhanced linearity sampled-data voltage amplifier

A sampled-data feedback circuit topology is presented for the implementation of an enhanced linearity voltage amplifier that does not require an operational amplifier in continuous-time feedback. By oversampling the analog input signal, nonlinearities and gain errors of the internal circuitry are overcome to obtain linearity beyond that of the individual components.