Arvin R. Shahani

A 12 mW wide dynamic range CMOS front end for a portable GPS receiver

At submicron channel lengths, CMOS is an attractive alternative to silicon bipolar and GaAs MESFET technologies for use in wireless receivers. A 12mW Global Positioning System (GPS) receiver front-end, comprising a low noise amplifier (LNA) and mixer implemented in a standard 0.35/spl mu/m digital CMOS process, demonstrates the aptitude of CMOS for portable wireless applications.

A 115-mW, 0.5-/spl mu/m CMOS GPS receiver with wide dynamic-range active filters

This paper presents a 115-mW Global Positioning System radio receiver that is implemented in a 0.5-/spl mu/m CMOS technology. The receiver includes the complete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-chip active filters, and 1-bit analog-digital converters. In addition, it includes a low-power phase-locked loop that synthesizes the first local oscillator. The receiver achieves a 2.8-dB noise figure (prelimiter), a 56-dB spurious-free dynamic range, and a 17-dB signal-to-noise ratio for a noncoherent digital back-end implementation when detecting a signal power of -130 dBm at the radio-frequency input.

A 115 mW CMOS GPS receiver

The Global Positioning System (GPS) provides accurate positioning and timing information that is useful in many applications. In particular, portable consumer GPS applications require cheap compact low-power receivers. This 115 mW receiver, implemented in an analog 0.5 /spl mu/m CMOS technology, comprises the entire radio-frequency (RF) and analog sections in addition to the local oscillator (LO) frequency synthesizer and a pair of oversampled A/D converters.

Low-power dividerless frequency synthesis using aperture phase detection

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eliminating the divider. The PLLs loop bandwidth is measured to he 6 MHz, with a reference spurious level of -47 dBc. The front-end receiver, including the synthesizer, is fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process and operates on a 2.5-V supply.

A 46-GHz distributed transimpedance amplifier using SiGe bipolar technology

In this work we present a transimpedance amplifier (TIA) with a typical 3-dB bandwidth of 46 GHz, suitable for 40 Gb/s data communication links, realized in a commercial SiGe BiCMOS technology. The amplifier uses a traveling-wave topology and achieves a typical transimpedance of 47 dB/spl Omega/ and a low input-referred current noise of 24 pA Hz/sup -0.5/ averaged between 0 and 40 GHz. The amplifier is especially designed to be integrated with a photodiode in a hybrid photoreceiver, using bond wire interconnects. A set of photoreceivers was successfully tested over a temperature range from 0 to 70 C. The low noise of the TIA results in a large dynamic range of the receivers and error-free operation was achieved up to an overload optical input power of more than +3 dBm.