Sunderarajan S. Mohan

Bandwidth extension in CMOS with optimized on-chip inductors

We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125-Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6-k/spl Omega/ transimpedance and a 0.6-/spl mu/A input-referred current noise, while operating with a photodiode capacitance of 0.6 pF. A fully differential topology ensures good substrate and supply noise immunity. The amplifier, implemented in a triple-metal, single-poly, 14-GHz f/sub Tmax/, 0.5-/spl mu/m CMOS process, dissipates 225 mW, of which 110 mW is consumed by the 50-/spl Omega/ output driver stage. The optimized on-chip inductors consume only 15% of the total area of 0.6 mm/sup 2/.

Optimization of inductor circuits via geometric programming

We present an efficient method for optimal design and synthesis of CMOS inductors for use in RF circuits. This method uses the the physical dimensions of the inductor as the design parameters and handles a variety of specifications including fixed value of inductance, minimum self-resonant frequency, minimum quality factor, etc. Geometric constraints that can be handled include maximum and minimum values for every design parameter and a limit on total area. Our method is based on formulating the design problem as a special type of optimization problem called geometric programming, for which powerful efficient interior-point methods have recently been developed. This allows us to solve the inductor synthesis problem globally and extremely efficiently. Also, we can rapidly compute globally optimal trade-off curves between competing objectives such as quality factor and total inductor area. We have fabricated a number of inductors designed by the method, and found good agreement between the experimental data and the specifications predicted by our method.

Design and optimization of LC oscillators

Presents a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular, the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal trade-off curves between competing objectives such as phase noise and power.

Modeling and characterization of on-chip transformers

We present a scalable analytical model for on-chip transformers that is suitable for design optimization and circuit simulation. We also provide simple and accurate expressions for evaluating the self inductance and the mutual coupling coefficient (k). The model agrees very well with measurements for a variety of transformer configurations.

A 115-mW, 0.5-/spl mu/m CMOS GPS receiver with wide dynamic-range active filters

This paper presents a 115-mW Global Positioning System radio receiver that is implemented in a 0.5-/spl mu/m CMOS technology. The receiver includes the complete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-chip active filters, and 1-bit analog-digital converters. In addition, it includes a low-power phase-locked loop that synthesizes the first local oscillator. The receiver achieves a 2.8-dB noise figure (prelimiter), a 56-dB spurious-free dynamic range, and a 17-dB signal-to-noise ratio for a noncoherent digital back-end implementation when detecting a signal power of -130 dBm at the radio-frequency input.

A 115 mW CMOS GPS receiver

The Global Positioning System (GPS) provides accurate positioning and timing information that is useful in many applications. In particular, portable consumer GPS applications require cheap compact low-power receivers. This 115 mW receiver, implemented in an analog 0.5 /spl mu/m CMOS technology, comprises the entire radio-frequency (RF) and analog sections in addition to the local oscillator (LO) frequency synthesizer and a pair of oversampled A/D converters.

Low-power dividerless frequency synthesis using aperture phase detection

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eliminating the divider. The PLLs loop bandwidth is measured to he 6 MHz, with a reference spurious level of -47 dBc. The front-end receiver, including the synthesizer, is fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process and operates on a 2.5-V supply.