Hirad Samavati

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.

A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc.

5-GHz CMOS wireless LANs

This paper first provides an overview of some recently ratified wireless local-area network (WLAN) standards before describing an illustrative 5-GHz WLAN receiver implementation. The receiver, built in a standard 0.25-/spl mu/m CMOS logic technology, exploits several recent developments, including lateral-flux capacitors, accumulation-mode varactors, injection-locked frequency dividers, and an image-reject low-noise amplifier. The receiver readily complies with the performance requirements of both IEEE 802.11a and ETSI HiperLAN. It exhibits a 7.2-dB noise figure, as well as an input-referred third-order intercept and 1-dB compression point of -7 and -18 dBm, respectively. Image rejection for this double conversion receiver exceeds 50 dB throughout the frequency band without using external filters. Leakage out of the RF port from the local oscillators is under -87 dBm, and all synthesizer spurs are below the -70-dBm noise floor of the instrumentation used to measure them. The receiver consumes 59 mW from a 1.8-V supply and occupies only 4 mm/sup 2/ of die area, in no small measure due to the use of fractal capacitors for ac coupling.

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.

A 115-mW, 0.5-/spl mu/m CMOS GPS receiver with wide dynamic-range active filters

This paper presents a 115-mW Global Positioning System radio receiver that is implemented in a 0.5-/spl mu/m CMOS technology. The receiver includes the complete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-chip active filters, and 1-bit analog-digital converters. In addition, it includes a low-power phase-locked loop that synthesizes the first local oscillator. The receiver achieves a 2.8-dB noise figure (prelimiter), a 56-dB spurious-free dynamic range, and a 17-dB signal-to-noise ratio for a noncoherent digital back-end implementation when detecting a signal power of -130 dBm at the radio-frequency input.

An 802.11g WLAN SoC

A single-chip IEEE 802.11g-compliant WLAN radio that implements all RF, analog, and digital PHY and MAC functions is implemented in a 0.18 /spl mu/m CMOS technology. The IC transmits 4 dBm EVM-compliant output power for a 64QAM OFDM signal. The overall receiver sensitivities are -95 dBm and -73 dBm for data rates 6 Mbit/s and 54 Mbit/s, respectively.

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN

A 2.4/5 GHz transceiver implements the RF and analog front-end of an IEEE 802.11a/g/b WLAN system in 0.25 /spl mu/m CMOS technology. The IC transmits 9 dBm/8 dBm EVM-compliant output power at 5 GHz/2.4 GHz for a 64QAM OFDM signal. The overall receiver NF is 5.5/4.5 dB at 5/2.4 GHz.

Reduction of Inductive Crosstalk Using Quadrupole Inductors

Interference due to inductor crosstalk is a growing concern in modern RFICs where inductors are placed in close proximity. A quadrupole inductor is explored as a method to reduce inductive crosstalk. A quadrupole inductor and standard inductor are compared with respect to inductance, quality factor, and area. Then, physics-based calculations are corroborated with simulation and measurement to predict crosstalk reduction as a function of position. Measurements verify up to a 31 dB reduction in crosstalk. Finally, phase noise measurements of voltage-controlled oscillators show that the quadrupole inductor can be used in circuits without negatively impacting performance.

A 1.9GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, fabricated in a 0.18mum CMOS process, implements all handset functions including radio, voice, audio, CPU, and digital interfaces. The IC has +4dBm EVM-compliant transmit power, -106dBm receiver sensitivity, and 15mus synthesizer settling time. It draws 81 mA from a 1.8V supply while occupying 35mm2 of chip area

A dual channel /spl Sigma//spl Delta/ ADC with 40MHz aggregate signal bandwidth

A dual-channel /spl Sigma//spl Delta/ ADC has been integrated in 0.13/spl mu/m CMOS technology with an oversampling ratio of 4. The ADC employs a cascade of low-pass and band-pass modulators and achieves an aggregate quadrature signal bandwidth of 40MHz at a sampling frequency of 160MS/s and 54dB dynamic range while dissipating 175mW from a 2.5V supply.