Arwa Ben Dhia

A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs

As CMOS feature sizes decrease into nanometers, manufacturing defects are becoming a growing concern in electronics industry. SRAM-based FPGAs, which have been widely used in many applications, are also affected by technology downscaling. Since the cornerstone of their logic and interconnect resources is the multiplexer, this work introduces a defect-tolerant multiplexer, more resilient to single transistor defects (stuck-open, stuck-closed and gate shorts) than other multiplexer architectures studied in the paper, and more area-efficient than other existent hardening techniques.

Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster

This paper proposes a method to analyze the effect of manufacturing defects and soft errors: stuck-ats and bit flips, on a cluster in a Mesh FPGA architecture. The cluster reliability is evaluated with a technique that is used in case of either a single error or multiple simultaneous faults. Simulation results show that the cluster is more robust to stuck-ats than to bit-flips, whatever the configuration memory is. Then, for selective hardening against bit flips, we propose an approach to identify the critical path and the most eligible component that is likely to improve the cluster reliability.

Cross logic: A new approach for defect-tolerant circuits

As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.

A defect-tolerant multiplexer using differential logic for FPGAs

As the dimensions of CMOS devices scale down to the nanometers, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we propose a defect-tolerant multiplexer architecture based on differential logic. This architecture proved to be more resilient to single defects (opens and bridges) than its single-ended standard counterpart and more compact than existing hardened architectures. The architectures were studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. Eventually, the robustness gain using differential logic was assessed for different sizes of FPGA look-up tables.

Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs

This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.

A defect-tolerant cluster in a mesh SRAM-based FPGA

In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intra-cluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost.

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA

Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This paper addresses a thoroughanalysis of the cluster size impact on area and routability ofthe cluster as well as on its testability and inherent robustness. Benchmark circuits are synthesized in a range of cluster sizes(number of logic blocks per cluster) 4, 6, 8, 10 and 12 to identifythe optimum one in terms of area and routability. Then, theoverall cluster testability and its respective cost is examinedusing BIST algorithm developed for this purpose. To completethe analysis, cluster size impact on the robustness of the clusterlogic and the intra-cluster interconnect is assessed by logicalmasking ability. Results show that the cluster of size 12 offers abetter routability at relatively less test cost along with a better robustness.

Evaluating CLB designs under multiple SETs in SRAM-based FPGAs

Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context, we are concerned about the susceptibility of SRAM-based FPGAs logic blocks to multiple single event transients. Our target is to select the most reliable CLB design among different architectures of hardened CLBs, under the constraint of limited overheads. After synthesizing the candidate CLB architectures in STM 65nm CMOS technology, we compare them in terms of logical masking and reliability, and evaluate their area, time and power overheads. The most reliable CLB design is selected according to a metric expressing the tradeoff between the reliability gain and the cost penalties.

Automatic selective hardening against soft errors: A cost-based and regularity-aware approach

This paper proposes a methodology to automatically apply selective hardening into a circuit based on the net hardening concept. Analysis is performed in the profile of a hardening cost function, in order to automatically determine a stop point for the hardening process. Such analysis can be, sometimes, very time consuming, and even intractable for large circuits. In order to overcome such limitation, two approaches are presented and combined in this paper. The first one takes advantage of circuit regularity, while the second limits the scope of the analysis. A set of circuits from the ISCAS85 benchmarks is used as case study. Simulation results demonstrate the effectiveness of the proposed methodology, where substantial reductions of the required computation time are achieved.

Improving the Robustness of a Switch Box in a Mesh of Clusters FPGA

As CMOS feature sizes are shrinking, manufacturing defects are becoming a growing concern in micro and nanoelectronics. This work deals with defect tolerance in FPGAs that are surely affected by technology downscaling. In this paper, we are interested in enhancing the defect tolerance of a switch box in a mesh of clusters FPGA, while trying to reduce the hardening cost. First, we had to spot, among the switch box multiplexers, the most eligible one to be hardened. Then, we built different possible architectures for the latter by assembling different standard cells from a 65nm industrial library. These architectures were studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. Eventually, the most robust architecture was picked.