Mariem Slimani

Multiple threshold voltage for glitch power reduction

We address the problem of circuit-level design for low power. We describe a new method for glitch power reduction based on threshold voltage adjustment. The proposed method achieves both dynamic and leakage power reductions. We develop an optimization algorithm that optimizes the circuit netlist to achieve glitch energy reductions without affecting the overall circuit delay requirement. Applying the algorithm to C17 benchmark circuit implemented in a 65nm industrial Low Power CMOS process, we have achieved 14% total energy savings and 78% leakage energy savings at the expense of just 5% delay increase.

Variability modeling in near-threshold CMOS digital circuits

Sub-threshold operation is an efficient solution for ultra low power applications. However, it is very sensitive to process variability which can impact the robustness and effective performance of the circuit. On the other hand, this sensitivity decreases toward near-threshold operation. In this paper, the impact of variability on sub-threshold and near-threshold circuit performance is investigated through analytical modeling and circuit simulation in a 65nm industrial low power CMOS process. It is shown that variability moves the effective minimum energy point toward the near-threshold region. Also, when variability is taken into account, a complete model including the region near-threshold (moderate inversion) is required to correctly model circuit performance around the minimum energy point. An analytical solution for the optimum supply voltage that minimizes the total energy per operation, while considering variability effects, is provided. Additionally, the resulting speed-consumption trade-off in a variability aware analysis of sub-threshold and near-threshold operation is presented. Graphical abstractDisplay Omitted HighlightsVariability is a strong limitation for sub and near-threshold digital CMOS.Variability moves the minimum energy point towards the near-threshold region.We propose a simple model for assessing the delay-energy trade-off with variability.The model is validated in a 32 bit adder and a 8 bit multiplier test cases.We derive an analytical solution of the VDD for minimum energy with variability.

A dual threshold voltage technique for glitch minimization

We propose to use dual-threshold voltage (dual-Vth) assignment for glitch reduction. We present a heuristic algorithm address this problem. Experimental results on 6 ISCAS85 benchmark circuits implemented in a 65 nm industrial low power CMOS process report more than 16% of glitch reduction on average, and up to 41% for C432 benchmark circuit. To further minimize glitches, we propose to unify gate-sizing and dual-Vth techniques into a single optimization process. Results show an improvement of 10% on average compared to the conventional gate-sizing method. Spice simulations of C432 benchmark circuit report more than 27% and 48% total energy reduction by means the proposed dual-Vth and dual-Vth/gate-sizing algorithm, respectively.

Variability-speed-consumption trade-off in near threshold operation

Sub-threshold operation is an efficient solution for ultra low power applications. However, it is very sensitive to process variability which can impact the robustness and effective performance of the circuit. On the other hand this sensitivity decreases as we move towards near-threshold operation. n this paper, the impact of variability on sub-threshold and nearthreshold circuit performance is investigated through analytical modeling and circuit simulation in a 65 nm industrial low power CMOS process.We show that variability moves the effective minimum energy point towards the near threshold region. Thus, we demonstrate that when variability is taken into account, a complete model that includes the near threshold (moderate inversion) region is necessary in order to correctly model circuit performance around the minimum energy point. Finally, we present the resulting speed-consumption trade-off in a variability-aware analysis of sub-threshold and near-threshold operation.

Cross logic: A new approach for defect-tolerant circuits

As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation using CMOS cells from a 65nm industrial process, that the proposed logic turns out to be a good compromise to construct robust circuits under the constraint of limited area overhead.

A defect-tolerant multiplexer using differential logic for FPGAs

As the dimensions of CMOS devices scale down to the nanometers, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we propose a defect-tolerant multiplexer architecture based on differential logic. This architecture proved to be more resilient to single defects (opens and bridges) than its single-ended standard counterpart and more compact than existing hardened architectures. The architectures were studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. Eventually, the robustness gain using differential logic was assessed for different sizes of FPGA look-up tables.

A tool for transient fault analysis in combinational circuits

With technology downscaling, the vulnerability of combinational logic circuits to transient faults has increased resulting in error rates approaching those of memories. Thus, to guarantee a good use of selective hardening techniques, fast and accurate approaches for transient fault analysis in logic circuits are needed. In this work, we describe a methodology for Soft Error Rate (SER) evaluation in combinational logic circuits that manages the dependency of logical and electrical masking effects in case of reconvergent fanouts. The approach combines analytical transient fault propagation model and fault simulation to speed up simulations.

A novel analytical method for defect tolerance assessment

Due to technology downscaling, defect tolerance analysis has become a major concern in the design of digital circuits. In this paper, we present a novel analytical method that calculates the defect tolerance of logic circuits using probabilistic defect propagation. The proposed method is explained in case of single defect model, but can be easily adapted to handle multiple fault scenarios. The approach manages signal dependencies due to reconvergent fanouts and provides accurate results while keeping linear complexity.

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters

Majority voters are typically used in redundancy hardening techniques aiming to increase the reliability of nanoscale circuits. Besides, Spin Transfer Torque Magnetic Tunnel Junction (STT-MJT) has been identified as the most promising candidate for low power and high speed applications. In this paper, we present two majority voter circuits based on nanometer STT-MTJ. By using STMicroelectronics FDSOI 28 nm process and a precise STT-MTJ compact model, electrical simulations have been carried out to compare their performances and analyze their reliability. Both radiation sensitivity and variability have been investigated in the reliability-aware analysis.

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI

Due to the process variation, Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) faces great challenges in fabrication process. Meanwhile, its neighbor CMOS is also influenced by significant process variation with the continuous technology scaling down. Both of the two effects lead to degraded performance of hybrid MTJ/CMOS circuit. This paper proposes a methodology to alleviate the impact of process variation on the performance of MTJ based applications. The methodology is presented by carrying out a novel design of non-volatile flip-flop (NVFF) using asymmetrical forward body bias (FBB) in fully depleted silicon on insulator (FDSOI). Simulation results show that the sensing errors have been almost removed by this method with the minimum size of circuit. In addition, the thermal robustness of this circuit has also been dramatically improved.