J.R. Watling

Si/SiGe heterostructure parameters for device simulations

This paper is based on a comprehensive review of the literature and our own studies. We present a summary of the theoretical models and related empirical expressions to evaluate parameters related to the carrier transport within Si/SiGe heterostructures. The models and expressions include the effects of alloy composition and mechanical strain on the band structure of Si/SiGe alloys and the corresponding interfaces. They are presented in a form suitable for implementation in various types of device simulators. Important parameters, such as the band structure of strained or relaxed SiGe, the conduction and valence band offsets in the Si1−xGex/Si1−yGey heterostructures, the effective transport masses and the densities of states, have been calculated and shown to be in good agreement with existing experimental and theoretical results. Analytical expressions of those parameters as a function of Ge composition of the SiGe alloy have been given for strained Si on relaxed Si1−yGey substrate and strained Si1−xGex on Si substrate.

Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study

It has recently become clear that the use of high-κ /metal gate stacks will have a distinct impact on the intrinsic parameter variability of the corresponding CMOS devices. The metal gates have a natural granularity, with the work function of each grain depending on its orientation. Here, we present a full-scale 3-D statistical simulation study of the statistical variability induced by this metal gate granularity (MGG). We investigate the effect of grain size on both the magnitude of the variability and the shape of the corresponding statistical distribution. The distributions in threshold voltage due to MGG are analyzed in isolation and in combination with random discrete dopants and line-edge roughness.

Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers

The room-temperature effective mobilities of pseudomorphic Si/Si0.64Ge0.36/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO2/Si interface roughness is a major source of scattering in these devices, which is attenuated for thicker silicon caps. It is also suggested that segregated Ge in the silicon cap interferes with the oxidation process, leading to increased SiO2/Si interface roughness in the case of thin silicon caps.

Quantum corrections in the simulation of decanano MOSFETs

Abstract Quantum mechanical confinement and tunnelling play an important role in present and future generation decanano (sub-100 nm) MOSFETs and have to be properly taken into account in the simulation and design. Here we present a simple approach of introducing quantum corrections in a 3D drift–diffusion simulation framework using the density gradient (DG) algorithm. We discuss the calibration of the DG approach in respect of quantum confinement effects in comparison with more comprehensive but computationally expensive quantum simulation techniques. We also speculate about the capability of DG to describe source-to-drain tunnelling in sub-10 nm (nano) MOSFETS. The application of the DG approach is illustrated with examples of 3D statistical simulations of intrinsic fluctuation effects in decanano and nano-scale double-gate MOSFETs.

The thermoelectric properties of Ge/SiGe modulation doped superlattices

The thermoelectric and physical properties of superlattices consisting of modulation doped Ge quantum wells inside Si1− y Ge y barriers are presented, which demonstrate enhancements in the thermoelectric figure of merit, ZT, and power factor at room temperature over bulk Ge, Si1− y Ge y , and Si/Ge superlattice materials. Mobility spectrum analysis along with low temperature measurements indicate that the high power factors are dominated by the high electrical conductivity from the modulation doping. Comparison of the results with modelling using the Boltzmann transport equation with scattering parameters obtained from Monte Carlo techniques indicates that a high threading dislocation density is also limiting the performance. The analysis suggests routes to higher thermoelectric performance at room temperature from Si-based materials that can be fabricated using micro- and nano-fabrication techniques.

The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices

As MOSFETs are scaled to sub 100 nm dimensions, quantum mechanical confinement in the direction normal to the silicon dioxide interface and tunnelling (through the gate oxide, band-to-band and from source-to-drain) start to strongly affect their characteristics. Recently it has been demonstrated that first order quantum corrections can be successfully introduced in self-consistent drift diffusion-type models using Quantum Potentials. In this paper we describe the introduction of such quantum corrections within a full 3D drift diffusion simulation framework. We compare the two most popular quantum potential techniques: density gradient and the effective potential approaches, in terms of their justification, accuracy and computational efficiency. The usefulness of their 3D implementation is demonstrated with examples of statistical simulations of intrinsic fluctuation effects in decanano MOSFETs introduced by discrete random dopants. We also discuss the capability of the density gradient formalism to handle direct source-to-drain tunnelling in sub 10 nm double-gate MOSFETS, illustrated in comparison with Non-Equilibrium Greens Functions simulations.

A study of the impact of dislocations on the thermoelectric properties of quantum wells in the Si/SiGe materials system

Thermoelectric materials generate electricity from thermal energy using the Seebeck effect to generate a voltage and an electronic current from a temperature difference across the semiconductor. High thermoelectric efficiency ZT requires a semiconductor with high electronic conductivity and low thermal conductivity. Here, we investigate the effect of scattering from threading dislocations of edge character on the thermoelectric performance of individual n and p-channel SiGe multiple quantum well structures. Our detailed physical simulations indicate that while the thermal and electrical conductivities decrease with increasing dislocation scattering/density, the Seebeck coefficient actually increases with increasing threading dislocation density above 106 cm−2 at room temperature, due to an increase in the entropy associated with each carrier. The collective result of these individual effects, is that the present Si-based quantum well designs can tolerate scattering by a threading dislocation density up to...

3-D Monte Carlo Simulation of the Impact of Quantum Confinement Scattering on the Magnitude of Current Fluctuations in Double Gate MOSFETs

For the scaling of ultrathin body double gate (UTB DG) MOSFETs to channel lengths below 10 nm, a silicon body thickness of less than 5 nm is required. At these dimensions the influence of atomic scale roughness at the interface between the silicon body and the gate dielectric becomes significant, producing appreciable body thickness fluctuations. These fluctuations result in a scattering potential related to the quantum confinement variation within the channel which, similarly to the interface roughness scattering, influences the mobility, the drive current and the intrinsic parameter variations. In this paper we have developed an ensemble Monte Carlo simulation approach to study the impact of quantum confinement scattering on the transport in sub-10 nm UTB DG MOSFETs, and the corresponding intrinsic parameter variations. By comparing the Monte Carlo simulations with drift-diffusion simulations we quantify the important contribution of the quantum confinement related scattering to the current fluctuations in such devices

Impact of single charge trapping in nano-MOSFETs-electrostatics versus transport effects

In this paper, using Monte Carlo (MC) simulations featuring ab initio Coulomb scattering, we study the impact of Coulomb scattering from a single trapped electron on the magnitude of the corresponding drain-current reduction in a series of well scaled n-channel nano-MOSFETs. Through a careful comparison with drift-diffusion (DD) simulations that only capture the electrostatic effects associated with the trapped charge, we were able to demonstrate the specific contribution of the scattering. The simulations are performed at low drain bias for MOSFETs with channel lengths of 30, 20, and 10 nm, respectively. Compared to the DD results, the MC simulations show significant additional reduction in drain current associated with the scattering from the trapped electron. The scattering related percentage reduction in the current increases with the increase of the gate voltage toward strong inversion conditions. The velocity distributions in the presence of the trapped charge at various gate conditions are carefully analyzed in order to explain the magnitude of the observed effect.

A 3-D Atomistic Study of Archetypal Double Gate MOSFET Structures

The double gate MOSFET architecture has been proposed as a possible solution to allow the scaling of MOSFETs to the sub-30 nm regime, particularly due to its inherent resistance to short-channel effects. The use of lightly doped, or even undoped, channels means that such devices should be inherently resistant to random dopant induced fluctuations which will be one of the major obstacles to MOSFET scaling towards the end of the Si Roadmap. Random dopants within the channel are not, however, the only source of intrinsic fluctuations within MOSFETs at this scale. In this paper we investigate the impact of discrete dopants in the source and drain, individual charges within the active region and line edge roughness on the intrinsic parameter fluctuations in double gate MOSFETs.