Ashish Lachhwani

A Distortion Compensating Flash Analog-to-Digital Conversion Technique

We present a flash ADC design technique that compensates for static nonlinearity of the up-front track-and-hold circuit, so that high speed and high linearity can be obtained at the same time. The proposed technique functions in synergy with a new background comparator offset correction scheme. The excess quantization noise generated due to the background autozero process is derived. We demonstrate the efficacy of our techniques with measurement results for a 160 MSPS 6-bit flash converter designed in a 0.35-mum CMOS process. The ADC consumes 50 mW from a 3.3 V power supply and has an 5.3 effective number of bits (ENOB) at Nyquist

A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain

We describe the design of a fifth order opamp-RC filter in a 65nm digital CMOS process. Designed for a WLAN receiver chain, the baseband filter has a bandwidth of 9MHz and features extensive use of digital hardware to correct for analog imperfections and thereby relaxing area and power requirements. Measurements show a 24 dB adjacent channel attenuation and an out-of-band IIP3 of 33 dBm. The complete filter consumes 9.5mA from a 1.3V supply and occupies an area of 0.46mm2.

An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor Scaling

In a charge-pump based type-II analog Phase Locked Loop (PLL), the loop filter often uses a small resistor along with a big integrating capacitor for good phase noise performance. This comes at the cost of large silicon area or external component. The noise from the resistor contributes to the output phase noise through both feedback and feed-forward paths and hence has a presence in the output over a very wide frequency band. In this PLL, the loop filter avoids the feed-forward and limits the contribution of the resistor noise over a narrow frequency band. This technique allows a large resistor to be used with a small capacitor without phase noise penalty. The achieved independent control of bandwidth and stabilizing zero gives better stability and reduces noise peaking. The integrated phase error achieved at 1.3GHz is -38dBc.