Subhashish Mukherjee

Codec for echo-canceling, full-rate ADSL modems

A codec, fabricated in 3.3 V CMOS, provides the low-voltage transmitter and receiver interfaces between DSP and high voltage hybrid circuit for either the central office (CO) or the remote terminal (RT), configurable by metal mask option. The die area is 67.5 square millimeters. The power dissipation is 600 mW (CO) and 760 mW (RT).

A fully integrated 2×2 b/g and 1×2 a-band MIMO WLAN SoC in 45nm CMOS for multi-radio IC

A significant increase in Smartphones and tablets with embedded Wi-Fi demands a low-cost system solution. In this paper the RF core of an 802.11n 2×2 b/g band, 2×1 a-band MIMO WLAN SoC with die area of 3.83mm2 in 45nm CMOS is described. As shown in Fig. 19.1.1 the SoC has integrated Power Amplifier (PA) for both bands and T/R switch in b/g band, eliminating the need for an expensive external Front-End Module. The LO is synthesized by a two-step DLL-PLL architecture to meet the stringent phase-noise requirements.

A 45nm CMOS near-field communication radio with 0.15A/m RX sensitivity and 4mA current consumption in card emulation mode

Near Field Communication (NFC) is an emerging technology that is penetrating the mobile phone market rapidly. Compliance to multiple NFC standards [1-3] requires designs to support wide dynamic range of field (0.15 to 12A/m), multiple data rates (1.65 to 848Kb/s), various modulation transition times (0.01 to 8usec), wide range of modulation indices (8 to 100%) and line coding techniques (Manchester, NRZ, Modified Miller and PPM). Also, support for small antenna size and very low power card emulation (tag) operation results in additional design constraints. The solution described here integrates all the NFC functions on a multi-IP connectivity SOC in 45nm CMOS.

A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain

We describe the design of a fifth order opamp-RC filter in a 65nm digital CMOS process. Designed for a WLAN receiver chain, the baseband filter has a bandwidth of 9MHz and features extensive use of digital hardware to correct for analog imperfections and thereby relaxing area and power requirements. Measurements show a 24 dB adjacent channel attenuation and an out-of-band IIP3 of 33 dBm. The complete filter consumes 9.5mA from a 1.3V supply and occupies an area of 0.46mm2.

A 115mW 12-bit 50 MSPS pipelined ADC

High sampling rate ADCs are needed in several communications applications like cable modems, and wireless LANs. In this paper we present a low power pipelined ADC cell implemented in a 0.18 /spl mu/m digital CMOS process. The ADC uses a 4-bit/stage architecture for reduced power and area. The ADC has been put on a test chip to verify performance and achieves -70dB THD performance for 10 MHz input at 50 MHz sampling rate.

A 2.5 V 10 bit SAR ADC

Presented here is a 10 bit SAR ADC working over a wide supply range of 5.5 V to 2.5 V. The circuit is built in a CMOS process with Metal-Poly capacitors. Issues related to low voltage sampling circuitry design and low voltage high speed comparator design are discussed. Silicon evaluation results are presented.

25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS

Chip based digital isolators are being developed for higher speed and higher isolation capabilities [1, 2]. These make use of various coupling mechanisms such as capacitive coupling [3] and transformer coupling [4]. A limitation of these technologies is that they need to maintain a low separation (distance through insulation DTI<30µm) through high quality insulators (oxides, polyamides) in order to achieve data rate and isolation performance [2]. These require expensive special process development and special packaging techniques to meet reinforced isolation recommended by IEC 60747-5-5 and VDE 0884-10. Other high-speed die-to-die communication techniques implemented using millimeter-wave and optical solutions are expensive and not designed for isolation. In this work, an isolation technique is proposed where two standard 180nm CMOS dies placed side by side with DTI of more than 500µm, and co-packaged using regular planar MCM flow with package mold compound being the isolation material, achieve asynchronous bidirectional link with >24kV surge isolation capability and greater than 500Mb/s at 175pJ/b. Channel gain is maximized using resonance. Gain is decoupled from channel bandwidth by resetting the channel state variables. This helps in enhancing data rate well beyond what is implied by the bandwidth.

Commercially Viable Ultra-Low Power Wireless

This chapter looks at various practical aspects of architecting and designing low power wireless radios and systems-on-chip for applications such as consumer wearables, industrial automation etc. The chapter starts with a discussion on the need for industry accepted protocols for low power wireless and aspects in these protocols that lend themselves to low power implementations. With these protocols in place, we then look at practical design techniques of the RF/analog components, followed by a look at the Physical layer and the MAC and conclude the section by looking at the overall SoC design techniques for proper energy management. The chapter concludes by looking at the upcoming IEEE 802.11ah standard and discuss how this is adapted in an advantageous manner for low power wireless applications.

Principal architectural changes in polar transmitter in DRP design for WLAN

In Digital Radio Processor(DRP) an All-digital Phase Locked Loop(ADPLL) forms the core of the architecture with a digitally controlled oscillator(DCO) being the counterpart of Voltage Controlled Oscillator (VCO) in a conventional PLL design. In addition to this, the RF modulation is also performed digitally by feeding Frequency Control Word(FCW) into the ADPLL. This implies that the DCO should be able to support the frequency range requirements for the modulation technique. DCO modulation range for GSM and Bluetooth systems is few hundreds of KHz. However, in order to support WLAN in both 2.4 GHz (ISM band) and 5–5.9 GHz(UNII) bands the DCO needs to have 1.2 GHz modulation range at 12 GHz frequency. Such a DCO becomes extremely sensitive to supply voltage fluctuations. We propose an algorithm which reduces the modulation range requirement of the DCO and hence its sensitivity to supply voltage. In DRP, the modulated clock output of the ADPLL is used as the sampling clock for the digital logic. For GSM and Bluetooth systems the drift introduced in phase samples by using the modulated clock is negligible. However, for WLAN, merely using the modulated clock for sampling is disastrous as it will introduce intolerable drift in the phase samples when compared to phase samples generated by using a constant uniform clock. We propose a predistortion scheme for frequency control words(FCW) to correct this effect of modulated clock.