Debapriya Sahu

A 90nm CMOS single-chip GPS receiver with 5dBm out-of-band IIP3 2.0dB NF

A single-chip GPS receiver with a low-IF heterodyne RF front-end includes a LNA, image-reject IQ mixers, a passive poly-phase filter, and a fully integrated synthesizer. The IF-strip consists of a jammer-reject filter, a VGA, a /spl Delta//spl Sigma/ ADC, and a digital IF-filter. The receiver dissipates 60 mA at 1.4 V and achieves a NF of 2 dB and out-of-band IIP3 of 5 dBm.

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒc, based on a input reference frequency ƒref. As part of the phase error measurement of the PLL, a Time to Digital converter(TDC) is used to measure the delay between ƒref clock edge and carrier clocking edge. An inverter chain is used to measure this delay as a integer number of basic inverter delay. This measurement error is termed TDC quantization error and effects the phase noise present in the final carrier. Due to the coarse delay of the basic inverter available, TDC introduces large quantization noise at the output of the PLL. This is too high for systems operating at high carrier frequencies or systems which have a tight phase noise requirement. This paper presents techniques to improve TDC quantization noise.

A fully integrated 2×2 b/g and 1×2 a-band MIMO WLAN SoC in 45nm CMOS for multi-radio IC

A significant increase in Smartphones and tablets with embedded Wi-Fi demands a low-cost system solution. In this paper the RF core of an 802.11n 2×2 b/g band, 2×1 a-band MIMO WLAN SoC with die area of 3.83mm2 in 45nm CMOS is described. As shown in Fig. 19.1.1 the SoC has integrated Power Amplifier (PA) for both bands and T/R switch in b/g band, eliminating the need for an expensive external Front-End Module. The LO is synthesized by a two-step DLL-PLL architecture to meet the stringent phase-noise requirements.

A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain

We describe the design of a fifth order opamp-RC filter in a 65nm digital CMOS process. Designed for a WLAN receiver chain, the baseband filter has a bandwidth of 9MHz and features extensive use of digital hardware to correct for analog imperfections and thereby relaxing area and power requirements. Measurements show a 24 dB adjacent channel attenuation and an out-of-band IIP3 of 33 dBm. The complete filter consumes 9.5mA from a 1.3V supply and occupies an area of 0.46mm2.

A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment

Describes the PLL designed for the analog front-end of the silicon tuner in the cable modem system. The PLL is used to generate clocks (150-175 MHz) for the DAC and hence the phase noise (jitter) requirement is very aggressive. Low noise design for all the main blocks was a key to achieve this. Care was taken to reduce reference spurs and supply/substrate injected spurs. The PLL uses two supplies. Charge pump and voltage controlled oscillator (VCO) work off a 3.3 V analog supply as it can give maximum VCO control voltage compliance, which helps reduce VCO gain, and hence reference and supply/substrate induced spurs. The digital part works off 1.8 V supply as 1.8 V core transistors give fastest switching which reduces phase noise in the dividers. The 3.3 V to 1.8 V interfaces have been optimized for the desired edges of output clock and phase comparison clock so that they have minimum contribution to phase error. Optimum loop bandwidth, PSRR and supply filtering were achieved to minimize phase noise and spurious modulation.

Principal architectural changes in polar transmitter in DRP design for WLAN

In Digital Radio Processor(DRP) an All-digital Phase Locked Loop(ADPLL) forms the core of the architecture with a digitally controlled oscillator(DCO) being the counterpart of Voltage Controlled Oscillator (VCO) in a conventional PLL design. In addition to this, the RF modulation is also performed digitally by feeding Frequency Control Word(FCW) into the ADPLL. This implies that the DCO should be able to support the frequency range requirements for the modulation technique. DCO modulation range for GSM and Bluetooth systems is few hundreds of KHz. However, in order to support WLAN in both 2.4 GHz (ISM band) and 5–5.9 GHz(UNII) bands the DCO needs to have 1.2 GHz modulation range at 12 GHz frequency. Such a DCO becomes extremely sensitive to supply voltage fluctuations. We propose an algorithm which reduces the modulation range requirement of the DCO and hence its sensitivity to supply voltage. In DRP, the modulated clock output of the ADPLL is used as the sampling clock for the digital logic. For GSM and Bluetooth systems the drift introduced in phase samples by using the modulated clock is negligible. However, for WLAN, merely using the modulated clock for sampling is disastrous as it will introduce intolerable drift in the phase samples when compared to phase samples generated by using a constant uniform clock. We propose a predistortion scheme for frequency control words(FCW) to correct this effect of modulated clock.

An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor Scaling

In a charge-pump based type-II analog Phase Locked Loop (PLL), the loop filter often uses a small resistor along with a big integrating capacitor for good phase noise performance. This comes at the cost of large silicon area or external component. The noise from the resistor contributes to the output phase noise through both feedback and feed-forward paths and hence has a presence in the output over a very wide frequency band. In this PLL, the loop filter avoids the feed-forward and limits the contribution of the resistor noise over a narrow frequency band. This technique allows a large resistor to be used with a small capacitor without phase noise penalty. The achieved independent control of bandwidth and stabilizing zero gives better stability and reduces noise peaking. The integrated phase error achieved at 1.3GHz is -38dBc.

nOHM/spl minus/a multi-process device synthesis tool for lateral DMOS structures

This paper presents a synthesis tool that generates layouts of Lateral Doubly-Diffused MOS (LDMOS) structures from electrical parameters of the device or from the current and thermal requirements of the package. Optionally, it generates layouts from physical parameters like DMOS width, area and floorplan constraints. Multiple layout and metal bus styles are supported. Source and drain sense DMOSs used to sample currents of the parent devices can also be generated and automatically placed inside the DMOS. The generated layouts are correct by construction. The tool has been developed for the Intelligent Power family of integrated circuits from Texas Instruments Inc. In this paper the need, capabilities and impact of the tool are presented along with the techniques used to achieve them.<<ETX>>