Atsuo Inoue

Ferroelectric Nonvolatile Memory Technology and Its Applications

Nonvolatile memory utilizing ferroelectric material is expected to be the ultimate memory due to its theoretical low power operation and fast access. We integrated a ferroelectric thin film using a standard complementary metal-oxide-semiconductor (CMOS) process and evaluated its basic characteristics and reliability including endurance and imprint effect. The film was prepared using a spin-on sol-gel method. A ferroelectric thin film formed using liquid source misted chemical deposition (LSMCD) was found to have almost the same characteristics as those of the film formed by the sol-gel method. No effects of the ferroelectric process on the CMOS transistors were observed. Design of ferroelectric memory cells and applications of the ferroelectric nonvolatile memory have been reviewed.

Temperature-dependent current-voltage characteristics of fully processed Ba0.7Sr0.3TiO3 capacitors integrated in a silicon device

Temperature-dependent current-voltage characteristics of fully processed Ba0.7Sr0.3TiO3 thin film capacitors integrated in a charge-coupled device delay-line processor as bypass capacitors were studied. The thin film capacitors with a film thickness of 185 nm were formed by metal-organic decomposition processing. The leakage current measured after completion of the integration process was 1 to 2 orders of magnitude higher than that measured after capacitor patterning. The leakage current at low voltages ( 10 V, 500 kV/cm), the Schottky mechanism plays a dominant role in leakage current, while the Frenkel-Poole emission begins to contribute to the leakage current as the temperature is elevated.

Time-dependent leakage current behavior of integrated Ba0.7Sr0.3TiO3 thin film capacitors during stressing

Time-dependent leakage current behavior of integrated Ba 0.7 Sr 0.3 TiO 3 capacitors accelerated by stresses in excess of operating temperature and voltage was studied. Current-voltage (J-V) studies revealed that the time-dependent leakage current behaviors are different according to the initial conduction process. When the initial leakage current of a fully processed integrated capacitor at high voltages at elevated temperatures is of the Frenkel-Poole emission type, the leakage current increases rapidly with time. The difference in the initial leakage currents is related to the difference in film growth conditions which determine the formation of defects in the films. The time-dependent increase in leakage current is ascribed to a change in the conduction mechanism from the interface-controlled Schottky type to the bulk-related space-charge-limited type due to the accumulation of oxygen vacancies near the cathode as a result of interface barrier lowering and the migration of distributed oxygen vacancies across the film.

SI LSI PROCESS TECHNOLOGY FOR INTEGRATING FERROELECTRIC CAPACITORS

The fabrication procedure of ferroelectric thin film capacitors onto conventional Si LSIs is investigated. Electrical characteristics of the integrated Ba1-x Srx TiO3 (BST) capacitors and the metal-oxide-semiconductor transistors embedded in the Si substrate are examined. Results of these measurements suggest the usefulness of this integration process for the fabrication of ferroelectric thin film devices, which is substantiated by the evaluation of an analog/digital IC with the integrated BST bypass capacitor.

2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

A neural network embedded processor with a dynamically reconfigurable pipeline architecture

A neural network embedded processor with a dynamically reconfigurable pipeline architecture is described. The processor dynamically changes connections between arithmetic units and memories to obtain the optimum pipeline configuration at every step of the network calculation. The processor attains a learning speed of 18 million connection updates per second (MCUPS), which is approximately 20 times that of the conventional digital signal processor. This processor provides expansibility in the calculation through a larger multilayer network by means of a network decomposition and a distributed processing approach.<<ETX>>