Hironori Yoshioka

Generation of very fast states by nitridation of the SiO2/SiC interface

Fast states at SiO2/SiC interfaces annealed in NO at 1150–1350 °C have been investigated. The response frequency of the interface states was measured by the conductance method with a maximum frequency of 100 MHz. The interface state density was evaluated based on the difference between quasi-static and theoretical capacitances (C−ψS method). Very fast states, which are not observed in as-oxidized samples, were generated by NO annealing, while states existing at an as-oxidized interface decreased by approximately 90%. The response frequency of the very fast states was higher than 1 MHz and increased when the energy level approaches the conduction band edge. For example, the response frequency (time) was 100 MHz (5 ns) at EC−ET = 0.4 eV and room temperature. The SiO2/SiC interface annealed in NO at 1250 °C showed the lowest interface state density, and NO annealing at a temperature higher than 1250 °C is not effective because of the increase in the very fast states.

Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance

We propose a method to accurately determine the surface potential (ψS) based on depletion capacitance, and the interface state density (DIT) was evaluated based on the difference between quasi-static and theoretical capacitances in SiC metal-oxide-semiconductor capacitors (C−ψS method). We determined that this method gives accurate values for ψS and DIT. From the frequency dependence of the capacitance measured at up to 100 MHz, a significant fast-interface-state response exists at 1 MHz, which results in the overestimation of ψS if it is determined based on the flatband capacitance at 1 MHz. The overestimation of ψS directly affects the accuracy of the energy level. DIT at a specific energy level is underestimated by the overestimation of ψS. Furthermore, the fast interface states that respond at 1 MHz cannot be detected by the conventional high(1 MHz)-low method. The C−ψS method can accurately determine the interface state density including the fast states without high-frequency measurements.

Effects of interface state density on 4H-SiC n-channel field-effect mobility

We investigated the effects of D IT at the interface between SiO2 and Si-, C-, and a-face 4H-SiC in n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) that were subjected to dry/nitridation and pyrogenic/hydrotreatment processes. D IT at E C − E T = 0.2 eV was evaluated by the C − ψ S method using MOS capacitors and was accurately reflected in the subthreshold slope of the MOSFETs. The peak field-effect mobility was inversely proportional to D IT. The mobility for the a-face MOSFETs was 1.5 times or more higher than the other faces mobilities, indicating that mobility limiting factors other than D IT(0.2 eV) may exist for the Si- and C-face interfaces.

N-channel field-effect mobility inversely proportional to the interface state density at the conduction band edges of SiO2/4H-SiC interfaces

We investigated the effects of the interface state density (D IT) at the interfaces between SiO2 and the Si-, C-, and a-faces of 4H-SiC in n-channel metal-oxide-semiconductor field-effect transistors that were subjected to dry/nitridation and pyrogenic/hydrotreatment processes. The interface state density over a very shallow range from the conduction band edge (0.00 eV < E C − E T) was evaluated on the basis of the subthreshold slope deterioration at low temperatures (11 K < T). The interface state density continued to increase toward E C, and D IT at E C was significantly higher than the value at the conventionally evaluated energies (E C − E T = 0.1–0.3 eV). The peak field-effect mobility at 300 K was clearly inversely proportional to D IT at 0.00 eV, regardless of the crystal faces and the oxidation/annealing processes.

Characterization of very fast states in the vicinity of the conduction band edge at the SiO2/SiC interface by low temperature conductance measurements

We have investigated the unique interface states (NI) generated by NO annealing at the SiO2/SiC interfaces by low-temperature conductance measurements, which is more suitable for characterization of very fast interface states than high-frequency conductance measurements at room temperature. Although only a part of the NI states can be evaluated by measurements at room temperature, the whole picture of the NI states, especially near the conduction band edge (0.07 eV ≤ EC−ET), has been revealed by the low temperature measurements. The NI peak was present at the interface even without NO annealing. The NI density increased with NO annealing temperature. The NI density at the energy levels shallower than 0.2 eV exceeded 1012 cm−2eV−1 after NO annealing. The capture cross section of the NI states is uniquely larger than that of conventional interface states.

Quantum-confinement effect on holes in silicon nanowires: Relationship between wave function and band structure

The authors theoretically studied the valence band structure and hole effective mass of rectangular cross-sectional Si nanowires (NWs) with the crystal orientation of [110], [111], and [001]. The E–k dispersion and the wave function were calculated using an sp3d5s∗ tight-binding method and analyzed with the focus on the nature of p orbitals constituting the subbands. In [110] and [111] nanowires, longitudinal/transverse p orbitals are well separated and longitudinal component makes light (top) subbands and transverse component makes heavy subbands. The heavy subbands are located far below the top light band when NW has square cross-section, but they gain their energy with the increase in the NW width and come near the band edge. This energy shift of heavy bands in [110] NWs shows strong anisotropy to the direction of quantum confinement whereas that in [111] NWs does not have such anisotropy. This anisotropic behavior and the difference among orientations are understandable by the character of the wave fu...

Mobility oscillation by one-dimensional quantum confinement in Si-nanowire metal-oxide-semiconductor field effect transistors

Si-nanowire p-channel metal-oxide-semiconductor field effect transistors (MOSFETs), in which the typical cross section of the nanowire is a rectangular shape with 3 nm height and 18 nm width, have been fabricated and the current-voltage characteristics have been measured from 101 to 396 K. The transconductance has shown oscillation up to 309 K. The carrier transport has been theoretically analyzed, assuming that the acoustic phonon scattering is dominant. The electronic states have been determined from the effective mass approximation and the mobility from the relaxation time approximation as a function of the Fermi level. Relation between the gate voltage and the Fermi level has been estimated from the MOSFET structure. The calculated mobility has shown the oscillation with change in the Fermi level (the gate voltage), resulting in the transconductance oscillation. The oscillation originates from one-dimensional density of states (∝E−0.5).

Bandgap shift by quantum confinement effect in 〈100〉 Si-nanowires derived from threshold-voltage shift of fabricated metal-oxide-semiconductor field effect transistors and theoretical calculations

Si-nanowire (Si-NW) MOSFETs, the cross-sectional size (square root of the cross-sectional area of NWs) of which was changed from 18 to 4 nm, were fabricated and characterized. Both n- and p-channel MOSFETs have shown a nearly ideal subthreshold swing of 63 mV/decade. The threshold voltage of n-/p-channel MOSFETs has gradually increased/decreased with decreasing the cross-sectional size. The bandgap shift from bulk Si has been derived from the threshold-voltage shift. The bandgap of Si-NWs was calculated by a density functional theory, tight binding method, and effective mass approximation. The calculated bandgap shows good agreement with that derived from threshold voltage. The theoretical calculation indicates that the bandgap is dominated by the cross-sectional size (area) and is not very sensitive to the shape within the aspect-ratio range of 1.0-2.5.

Enhanced Drain Current of 4 H-SiC MOSFETs by Adopting a Three-Dimensional Gate Structure

4H-SiC (0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a 3-D gate structure, which has a top channel on the (0001) face and side-wall channels on the {112macr0} face, have been fabricated. The 3-D gate structures with a 1-5-mum width and a 0.8- mum height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300degC. The fabricated MOSFETs have exhibited good characteristics: The I ON/I OFF ratio, the subthreshold swing, and V TH are 109, 210 mV/decade, and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1-mum-wide MOSFET is 16 times higher than that of a conventional planar MOSFET.

Reduction of interface states by hydrogen treatment at the aluminum oxide/4H-SiC Si-face interface

Processes to form aluminum oxide as a gate insulator on the 4H-SiC Si-face are investigated to eliminate the interface state density (D IT) and improve the mobility. Processes that do not involve the insertion or formation of SiO2 at the interface are preferential to eliminate traps that may be present in SiO2. Aluminum oxide was formed by atomic layer deposition with hydrogen plasma pretreatment followed by annealing in forming gas. Hydrogen treatment was effective to reduce D IT at the interface of aluminum oxide and SiC without a SiO2 interlayer. Optimization of the process conditions resulted in D IT for the metal oxide semiconductor (MOS) capacitor of 1.7×1012 cm−2eV−1 at 0.2 eV, and the peak field-effect mobility of the MOS field-effect transistor (MOSFET) was approximately 57 cm2V−1s−1.