Paolo Fantini

Unsupervised Learning by Spike Timing Dependent Plasticity in Phase Change Memory (PCM) Synapses

We present a novel one-transistor/one-resistor (1T1R) synapse for neuromorphic networks, based on phase change memory (PCM) technology. The synapse is capable of spike-timing dependent plasticity (STDP), where gradual potentiation relies on set transition, namely crystallization, in the PCM, while depression is achieved via reset or amorphization of a chalcogenide active volume. STDP characteristics are demonstrated by experiments under variable initial conditions and number of pulses. Finally, we support the applicability of the 1T1R synapse for learning and recognition of visual patterns by simulations of fully connected neuromorphic networks with 2 or 3 layers with high recognition efficiency. The proposed scheme provides a feasible low-power solution for on-line unsupervised machine learning in smart reconfigurable sensors.

Three-dimensional Poole-Frenkel analytical model for carrier transport in amorphous chalcogenides

In this work, we propose a three-dimensional Poole-Frenkel (3DPF) analytical model for carrier transport in amorphous chalcogenides. 3DPF is based on the original Poole-Frenkel (PF) theory of non-interacting Coulombic traps responsible for carrier conduction in the bulk of the material. However, while in the original PF equation the device current-voltage characteristics is calculated by considering the barrier-lowering on the applied electric field direction only, in 3DPF we overcome this approximation by calculating the electronic current due to the integral effect of the Coulombic barrier shaping in three dimensions upon application of an electric field. As a consequence, 3DPF is capable to describe both the relatively-low and relatively-high electric fields regimes, while the PF equation implicitly assumes the device to be operated at high electric fields only. Thus, 3DPF features a better agreement with experimental data compared to original PF, predicting both (i) Poole-like behavior at low-fields, ...

Modeling nand Flash Memories for IC Design

In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.

Characterization and modelling of low-frequency noise in PCM devices

Low-frequency noise in PCM devices is experimentally investigated providing a new physical model for the amorphous GST (Ge2Sb2Te5) material. Noise intensity is characterized and modelled as a function of bias, temperature and size. Findings from 1/f noise analysis are used to understand the drift mechanism of the amorphous state resistance.

Analytical model of deeply-scaled thyristors for memory applications

In this paper we propose an analytical model for the static operation of thyristor, aiming at clarifying the basic physics involved in the switching from the low-conductance to the high-conductance state of the device. Modeling results are compared to TCAD numerical simulations, showing that the analytical calculations can nicely reproduce the main features of the current-voltage device characteristics.

A Unified Hopping Model for Subthreshold Current of Phase-Change Memories in Amorphous State

The conduction process of phase-change-memory (PCM) devices in the amorphous high-resistance state is described by a trap-limited transport model. Based on numerical simulations of the barrier lowering in a potential landscape due to localized charged states, we propose a physically based analytical hopping model accounting for the different voltage dependence of current characteristics in the low- and high-field regimes. The analytical model is able to accurately describe, with the same set of parameters, the experimental behavior of both the temperature-dependent I- V curves and the voltage-dependent activation energy for conduction. Comparison with experimental data is provided, demonstrating the physical consistency of the proposed model.

Working Principles of a DRAM Cell Based on Gated-Thyristor Bistability

This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p-base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the p-base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast WRITE and READ operations with low voltage requirements.

Understanding Overreset Transition in Phase-Change Memory Characteristics

In a phase-change memory (PCM), the overreset phenomenon, namely, the resistance decrease at pulse amplitudes well beyond the reset current, may affect the resistance window and the device noise margin. We characterized overreset states in PCM devices by electrical testing and electron microscopy. Our analysis shows that overreset programmed cell presents changes in the electronic band structure of the amorphous phase, with no degradation in the programmed amorphous volume.

Dynamic Analysis of Current-Voltage Characteristics of Nanoscale Gated-Thyristors

This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.

Compact Modeling of Variability Effects in Nanoscale nand Flash Memories

This paper presents a thorough investigation of the main variability effects in nanoscale nand Flash memories, considering their impact on device operation by means of a statistical compact model for the memory array. The compact model allows the accurate simulation not only of the nand string current in read conditions, including parasitic capacitive couplings among neighboring cells, but also of cell program and erase. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of both neutral and programmed cell threshold voltage is obtained for state-of-the-art and next-generation technology nodes. The good agreement between modeling and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on nand technology design.