Augusto Ronchini Ximenes

A 0.034mm 2 , 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.

A 256×256 45/65nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications with optical polar modulation for up to 18.6dB interference suppression, 2018 IEEE International Solid - State Circuits Conference - (ISSCC)

Light detection and ranging (LiDAR) systems based on direct time-of-flight (DTOF) are used in spacecraft navigation, assembly-line robotics, augmented and virtual reality (AR/VR), (drone-based) surveillance, advanced driver assistance systems (ADAS), and autonomous cars. Common requirements are accuracy and speed, while ensuring long operating distance, high tolerance to background illumination and robustness to interference from other LiDAR systems. To meet these demands, the DTOF sensor community has provided numerous architectures, typically making use of resource sharing that often introduces tradeoffs between pixel count and speed. If resource sharing is not used, reduced fill factor, high non-uniformity, and pile-up distortion generally arise, thus limiting overall performance [1].

A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology, 2017 IEEE International Electron Devices Meeting (IEDM)

We report on the worlds first back-illuminated 3D-stacked single-photon avalanche diode (SPAD) in 45nm CMOS technology. This SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420–920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage and room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3D-stacked SPAD technology.

Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors

Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase/delay-locked loops (PLLs/DLLs). Other methods, such as relative timing measurement (start/stop), require constant foreground calibration, which is not feasible for outdoor applications, where conditions of temperature, background illumination, etc. can change drastically and frequently. In this paper, a scalable reference generation and synchronization is provided, using minimum resources of area and power, while being robust to mismatches. The suitability of this approach is demonstrated through the design of an 8×8 time-to-digital converter (TDC) array, distributed over 1.69 mm2, fabricated using TSMC 65 nm technology (1.2 V core voltage and 4 metal layers—3 thin + 1 thick). Each TDC is based on a ring oscillator (RO) coupled to a ripple counter, occupying a very small area of 550 μm2, while consuming 500 μW of power, and has 2 μs range, 125 ps least significant bit (LSB), and 14-bit resolution. Phase and frequency locking among the ROs is achieved, while providing 18 dB phase noise improvement over an equivalent individual oscillator. The integrated root mean square (RMS) jitter is less than 9 ps, the instantaneous frequency variation is less than 0.11%, differential nonlinearity (DNL) is less than 2 LSB, and integral nonlinearity (INL) is less than 3 LSB.

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

In this paper, we apply various area reduction techniques on an inductor–capacitor (LC)-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact split transformer topology that provides a 1:2 passive voltage gain and is less susceptible to common-mode electromagnetic interference than are regular high-quality-factor LC tanks, thus making it desirable in system-on-a-chip environments. The oscillator, together with a proposed dc-coupled buffer, is incorporated within an all-digital phase-locked loop (ADPLL) intended for wireline, digital clocking, and less stringent wireless systems. The ADPLL architecture introduces a look-ahead time-to-digital converter that exploits a deterministic phase prediction to reduce power consumption and phase detection complexity. The ADPLL is realized in 40-nm CMOS and has the smallest reported area of 0.0625 mm2 among LC-tank oscillators while providing fractional-N operation, wide tuning range of 45% (from 9.4 to 14.8 GHz), very low voltage supply sensitivity of 80 MHz/V, and integrated figure-of-merit jitter (FoMjitter) better than −230 dB. A separate identical ADPLL was implemented using an RO instead, for completeness and systematic comparisons.