Tzu-Jui Wang

High performance 300mm backside illumination technology for continuous pixel shrinkage

Backside Illumination (BSI) sensor with excellent optical performance has become the main-stream CMOS image sensor process. This work addressed the key factors and issues for 300mm BSI technology, including wafer distortion, silicon thickness variation, backside junction formation and dielectric film structure, thermal annealing and so on. It is demonstrated that with the optimized key process, a high performance 0.9um BSI pixel with low noise can be fabricated.

A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology, 2017 IEEE International Electron Devices Meeting (IEDM)

We report on the worlds first back-illuminated 3D-stacked single-photon avalanche diode (SPAD) in 45nm CMOS technology. This SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420–920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage and room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3D-stacked SPAD technology.

A dead-time free global shutter CMOS image sensor with in-pixel LOFIC and ADC using pixel-wis e connections

An almost 100% temporal aperture (dead-time free) global shutter (GS) stacked CMOS image sensor (CIS) with in-pixel lateral overflow integration capacitor (LOFIC), ADC and DRAM is developed using pixel-wise connections. The prototype chip with 6.6μm-pitch VGA LOFIC pixel dead-time free GS mode and 1.65μm-pitch 4.9M sub-pixel high resolution rolling shutter (RS) mode was fabricated with a 45nm 1P4M CIS technology for PD substrate and a 65nm 1P5M CMOS technology for ASIC substrate.