Yuichiro Yamashita

A 300mm wafer-size CMOS image sensor with in-pixel voltage-gain amplifier and column-level differential readout circuitry

Large-format image sensors provide us with a new form of vision in several areas such as astronomy and industry. The sensors commonly comprise thin-film transistors (TFTs) and photodiodes (PDs) on amorphous silicon. The capabilities of the amorphous silicon sensors, however, are insufficient due to the low carrier mobility of the TFTs. Recently several large-format CCDs [1] and CMOS image sensors [2,3] have been developed on crystal silicon wafers for faster readout speed, reduced image lag, high sensitivity and reduced noise.

A 256×256 45/65nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications with optical polar modulation for up to 18.6dB interference suppression, 2018 IEEE International Solid - State Circuits Conference - (ISSCC)

Light detection and ranging (LiDAR) systems based on direct time-of-flight (DTOF) are used in spacecraft navigation, assembly-line robotics, augmented and virtual reality (AR/VR), (drone-based) surveillance, advanced driver assistance systems (ADAS), and autonomous cars. Common requirements are accuracy and speed, while ensuring long operating distance, high tolerance to background illumination and robustness to interference from other LiDAR systems. To meet these demands, the DTOF sensor community has provided numerous architectures, typically making use of resource sharing that often introduces tradeoffs between pixel count and speed. If resource sharing is not used, reduced fill factor, high non-uniformity, and pile-up distortion generally arise, thus limiting overall performance [1].

A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology, 2017 IEEE International Electron Devices Meeting (IEDM)

We report on the worlds first back-illuminated 3D-stacked single-photon avalanche diode (SPAD) in 45nm CMOS technology. This SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420–920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage and room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3D-stacked SPAD technology.

A dead-time free global shutter CMOS image sensor with in-pixel LOFIC and ADC using pixel-wis e connections

An almost 100% temporal aperture (dead-time free) global shutter (GS) stacked CMOS image sensor (CIS) with in-pixel lateral overflow integration capacitor (LOFIC), ADC and DRAM is developed using pixel-wise connections. The prototype chip with 6.6μm-pitch VGA LOFIC pixel dead-time free GS mode and 1.65μm-pitch 4.9M sub-pixel high resolution rolling shutter (RS) mode was fabricated with a 45nm 1P4M CIS technology for PD substrate and a 65nm 1P5M CMOS technology for ASIC substrate.