Sana Rezgui

Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

This paper investigates an approach to study the effects of upsets on the operation of microprocessor-based digital architectures. The method is based on the injection of bit-flips, randomly in time and location by using the capabilities of typical application boards. Experimental results, obtained on programs running on two different digital boards, built around an 80C51 microcontroller and a 320C50 Digital Signal Processor, illustrate the potentialities of this new strategy.

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

Heavy-ion irradiation and fault injection experiments were conducted to evaluate the upset sensitivity of the Xilinx Virtex-II field programmable gate arrays (FPGAs) input/output block (IOB). Full triple module redundancy (TMR) of the IOBs, in combination with regular configuration scrubbing, proved to be a quite effective upset mitigation method.

Estimating error rates in processor-based architectures

This paper investigates a new technique to predict error rates in digital architectures based on microprocessors. Three studied cases are presented concerning three different processors. Two of them are included in the instruments of a satellite project. The actual space applications of these two instruments were implemented using the capabilities of a dedicated system. Results of the fault injection and radiation testing experiments and discussions about the potentialities of this technique are presented.

Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

We compare four circuit methods for single event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and triple modular redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA architecture which can be configured based on SE mitigation and performance needs, and we evaluate the candidate SE mitigation methods as to suitability for such architecture.

Investigation of Low Dose Rate and Bias Conditions on the Total Dose Tolerance of a CMOS Flash-Based FPGA

TID test results of CMOS Flash-based FPGAs in gamma-rays are presented. The use of realistic low dose-rates and oriented bias-conditions are shown to extend the FPGA TID tolerance. Implications to qualification methods and to most of the new CMOS technologies are noted.

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Results from fault injection experiments on a modern complex processor, the PPC7400, are combined with static register ground testing to predict single-event upset rates of several benchmark application programs. These results compare favorably with in-beam measurements on the same programs.

Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied

The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and limitations of the studied approach.

New Methodology for Simulation of Soft Errors in Digital Processors

Development and implementation are presented of a new fault injection technique for error rate prediction of processor-based digital architectures operating under radiation. Bit e ips are injected in potentially sensitive memory locations concurrently with the execution of a program. The error rate derived from those fault injection experiments and the underlying cross section of the studied processor will allow the cross section estimation of this circuit running a given program. A comparative analysis of experimental results issued from both soft error injection and ground testing under radiation performed on a board built around a microprocessor demonstrates the efe ciency of this new technique to predict the error rate of an application.

Error rate estimation for a flight application using the CEU fault injection approach

This paper aims at validating the efficiency of a fault injection approach to predict error rate on applications devoted to operate in radiation environment. Soft error injection experiments and radiation ground testing were performed on software modules using a digital board built on a digital signal processor which is included in a satellite instrument. The analysis of experimental results put in evidence the potentialities offered by the used methodology to predict the error rate of complex applications.