Carl Carmichael

The rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs

Results are presented from real-time experiments that evaluated large field programmable gate arrays (FPGAs) fabricated in different CMOS technologies (0.15 /spl mu/m, 0.13 /spl mu/m, and 90 nm) for their sensitivity to radiation-induced single-event upsets (SEUs). These results are compared to circuit simulation (Qcrit) studies as well as to Los Alamos Neutron Science Center (LANSCE) neutron beam results and Crocker Nuclear Laboratory (University of California, Davis) cyclotron proton beam results.

SEU mitigation testing of Xilinx Virtex II FPGAs

SRAM-based reconfigurable programmable logic is widely used in commercial applications and occasionally used in space flight applications because of susceptibility to single-event upset (SEU). Upset detection and mitigation schemes have been tested on the Xilinx Virtex II X-2V1000 in heavy-ion and proton irradiation to control the accumulation of SEUs and to mitigate their effects on the intended operation. Non-intrusive upset detection and partial reconfiguration in combination with TMR can repair the design to maintain state information. In-beam results on a simple test design demonstrate the effectiveness of these methods when used together.

Monte-Carlo Based On-Orbit Single Event Upset Rate Prediction for a Radiation Hardened by Design Latch

Heavy ion cross section data taken from a hardened-by-design circuit are presented which deviate from the traditional single sensitive volume or classical rectangular parallelepiped model of single event upset. TCAD and SPICE analysis demonstrate a SEU mechanism dominated by multiple node charge collection. Monte Carlo simulation is used to model the response and predict an on-orbit error rate.

Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions

A comparison of heavy-ion and proton-induced single event effect sensitivities has been made using the Xilinx Virtex-II field programmable gate array (FPGA). Recently fabricated test samples are selected for observations of single event upset and single event functional interrupt. A complex relationship appears to exist between the heavy ion and proton sensitivities due to effects such as multiple-bit upsets and elastic nuclear scattering.

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

Heavy-ion irradiation and fault injection experiments were conducted to evaluate the upset sensitivity of the Xilinx Virtex-II field programmable gate arrays (FPGAs) input/output block (IOB). Full triple module redundancy (TMR) of the IOBs, in combination with regular configuration scrubbing, proved to be a quite effective upset mitigation method.

Single Event Upsets in Xilinx Virtex-4 FPGA Devices

We present single event upset sensitivities for three Xilinx Virtex-4 field-programmable-gate-array (FPGA) devices in protons and heavy ions. Upsets are identified in each functional block and results compared with previous device generations

Static Upset Characteristics of the 90nm Virtex-4QV FPGAs

Radiation Test Consortium (XRTC) single-event measurements for three of the latest generation of radiation-tolerant reconfigurable FPGAs from Xilinx (90 nm, copper- interconnected, thin-epitaxial CMOS) are presented. Results include proton and heavy-ion upset susceptibilities for unclocked memory elements, high-temperature latchup immunity and a low SEFI rate (e.g., ~one/device-century in geosynchronous orbit).

Single-Event Upset (SEU) Results of Embedded Error Detect and Correct Enabled Block Random Access Memory (Block RAM) Within the Xilinx XQR5VFX130

Recent heavy ion measurements of the single-event upset (SEU) cross section for 65 nm embedded block random access memory (Block RAM) are presented. Results of initial investigation into the on-chip Error Detection and Correction (EDAC) are also discussed.

Heavy ion characterization of SEU mitigation methods for the Virtex FPGA

This work presents the results from heavy ion tests of Xilinx Virtex FPGA XQVR300 manufactured by Xilinx in a 0.25/spl mu/m technology. Virtex XQVR300 is an SRAM-based FPGA, which allows for real-time reconfigurable computing. Reprogrammable logic would offer the benefit of on-orbit design changes. Earlier SEU testing on this type of device has reported high sensitivity to heavy ions. Mitigation techniques of single event upsets in Virtex devices as triple module redundancy (TMR) and configuration readback (bitstream repair) have been developed by Xilinx and are tested in this work.

Complex upset mitigation applied to a Re-configurable embedded processor

Soft-core processors implemented in static random access memory-based field-programmable-gate-arrays, while attractive to spacecraft designers, require upset mitigation. We investigate a proposed solution involving two levels of scrubbing plus triple modular redundancy and measure its in-beam performance.